Unidirectional clock signaling in a high-speed serial link

ABSTRACT

Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 62/289,874, entitled “SCALABLE, HIGH-EFFICIENCY, HIGH-SPEEDSERIALIZED INTERCONNECT” and filed on Feb. 1, 2016, and the benefit ofU.S. Provisional Application Ser. No. 62/290,309, entitled “TRANSCEIVERFOR WIRELESS BASEBAND DIGITAL INTERCONNECT” and filed on Feb. 2, 2016,and the benefit of U.S. Provisional Application Ser. No. 62/290,357,entitled “TESTING OF A TRANSCEIVER FOR WIRELESS BASEBAND DIGITALINTERCONNECT” and filed on Feb. 2, 2016, all of which are expresslyincorporated by reference herein in its entirety.

BACKGROUND

Field

The present disclosure relates generally to interconnect systems, andmore particularly, to a high-speed serial interconnect system.

Background

Electronic devices are typically made up of multiple systems built onintegrated circuits (ICs), e.g., silicon chips. The different IC systemscan be specialized to handle different functions of the electronicdevice. For example, a mobile communications device can include an ICsystem for processing radio frequency (RF) signals received andtransmitted through various antennas. The RF antennas in a cell phone,for example, can include antennas to receive and transmit cellcommunication signals, to receive global positioning system (GPS)signals, etc. The task of processing RF signals received and transmittedby the cell phone can be performed by a radio frequency integratedcircuit (RFIC), which may include, for example, power amplifiers (PA),low-noise amplifiers (LNAs), antenna tuners, filters, sensors, powermanagement devices, switches, etc. On the other hand a different ICsystem, typically called a baseband modem or baseband IC (BBIC), canhandle the task of sorting out the various incoming and outgoing RFcommunications and sending each one to the proper destination (e.g., anincoming GPS signal might be sent to a GPS IC, an incoming cellcommunication might be parsed into data and voice and sent to theappropriate data processing IC and voice processing IC).

The different IC systems communicate with each other via signal lines.For example, some IC systems can be built as separate IC chips, whichcan be connected together by soldering them to the same printed circuitboard (PCB). In this case, the printed wires on the PCB can serve as thesignal lines between the different IC systems on separate chips. Inanother example, multiple systems can be built on a single IC, which canbe referred to as a system-on-a-chip (SoC). In this case, conductivepathways built into the IC chip can serve as the signal lines.

Communication between system ICs is performed using a communicationinterface, which defines how data is sent and received via the signallines. In many applications, serial interfaces have become the preferredmethod for digital communication between IC systems. Serialcommunication is the process of sending data one bit at a time,sequentially, over a communication channel, such as signal lines. Thisis in contrast to parallel communication, where several bits are sent asa whole, on a link with several parallel channels. An interconnect orlink is a point-to-point communication channel between two portsallowing both of them to send and receive data and messages. Serialinterconnects are becoming more common at shorter distances, as improvedsignal integrity and transmission speeds in newer serial technologieshave begun to outweigh the parallel bus's advantage of simplicity (e.g.,no need for serializer and deserializer, or SERDES) and to outstrip itsdisadvantages (e.g., clock skew, interconnect density).

As the speed of data communication increases, so does the power neededto communicate over serial interconnects. In battery-operated devices,such as mobile devices, low power operation is critical to allow longeroperation between charges. However, as the need for faster and fasterdata communication speeds has grown, it has become challenging forserial interconnects to provide the accuracy (e.g., low error rate)required for high-speed communication while operating at a low power.

SUMMARY

The following presents a simplified summary of one or more aspects inorder to provide a basic understanding of such aspects. This summary isnot an extensive overview of all contemplated aspects, and is intendedto neither identify key or critical elements of all aspects nordelineate the scope of any or all aspects. Its sole purpose is topresent some concepts of one or more aspects in a simplified form as aprelude to the more detailed description that is presented later.

In various embodiments, unidirectional clock signaling is used fortransmission of data over a serial link. A master device can generate aunidirectional clock signal based on a first clock of the master device.In some embodiments, the unidirectional clock signal can be generated tohave the same rate as the first clock. In some embodiments,unidirectional clock signal is generated such that a rate of theunidirectional clock signal is a fraction of a rate of the first clock.The master device can send the unidirectional clock signal to a slavedevice that is connected to the serial link. The master device cantransmit data to the slave device over the serial link based on thefirst clock. In some embodiments, the unidirectional clock signal can besent over the serial link to the slave device. In some embodiments, theunidirectional clock signal can be sent over a sideband to the slavedevice.

In various embodiments, a slave device can receive a unidirectionalclock signal from a master device. The unidirectional clock signal canbe based on a first clock of the master device. The slave device cantransmit data over the serial link to the master device based on theunidirectional clock signal. In some embodiments, the rate of theunidirectional clock can be the same as a rate of the first clock. Insome embodiments, the rate of the unidirectional clock signal can be afraction of a rate of the first clock. In some embodiments, theunidirectional clock signal can be received over the serial link fromthe master device. In some embodiments, the unidirectional clock signalcan be received over a sideband from the master device.

In various embodiments, an apparatus that transmits data over a seriallink can include a master device that includes a first clock, a clocksignal generator that generates a unidirectional clock signal based onthe first clock, and a transmitter component. In some embodiments, theclock signal generator can generate the unidirectional clock to have asame rate as the first clock. In some embodiments, the clock signalgenerator can generate the unidirectional clock such that a rate of theunidirectional clock signal is a fraction of a rate of the first clock.The transmitter component can send the unidirectional clock signal to aslave device that is connected to the serial link. The transmittercomponent can also transmit data to the slave device over the seriallink based on the first clock. In some embodiments, the transmittercomponent can transmit the unidirectional clock signal over the seriallink to the slave device. In some embodiments, the transmitter componentcan transmit the unidirectional clock signal over a sideband to theslave device.

In various embodiments, an apparatus that transmits data over a seriallink can include a slave device that includes a receiver that canreceive a unidirectional clock signal from a master device. Theunidirectional clock signal can be based on a first clock of the masterdevice. The slave device can also include a transmitter that cantransmit data over the serial link to the master device based on theunidirectional clock signal. In some embodiments, the rate of theunidirectional clock can be the same as a rate of the first clock. Insome embodiments, the rate of the unidirectional clock signal can be afraction of a rate of the first clock. In some embodiments, the receivercan receive the unidirectional clock signal over the serial link fromthe master device. In some embodiments, the receiver can receive theunidirectional clock signal over a sideband from the master device.

The following description and the annexed drawings set forth in detailcertain illustrative features of one or more aspects of the disclosure.These features are indicative, however, of but a few of the various waysin which the principles of various aspects may be employed, and thisdescription is intended to include all such aspects and theirequivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates various aspects of the disclosure in an exampleimplementation of a cell phone.

FIG. 2 illustrates an example of a transceiver apparatus that transmitsand receives signals across a high-speed serial link based onunidirectional clock signaling.

FIG. 3 illustrates an example SERDES transceiver configuration for aserial interconnect that communicates high-speed serial data based onunidirectional clock signaling.

FIG. 4 is a flowchart of an example method of a master connected to aserial link for performing unidirectional clock signaling according tovarious embodiments.

FIG. 5 is a flowchart of an example method of a slave connected to aserial link for performing unidirectional clock signaling.

FIG. 6 is a diagram illustrating an example operation performed over aserial interconnect system.

FIG. 7 is a diagram illustrating an example of a high-bandwidth,low-latency serial interconnect system.

FIG. 8 is a diagram illustrating a layered model that implements aserial interconnect system.

FIG. 9 is a diagram illustrating example packet structures of two typesof fixed-length packets.

FIG. 10 is a diagram illustrating an example packet burst structure atthe physical layer.

FIG. 11 is diagram illustrating an example 128/130b encoding of messageand data packet at the physical layer.

FIG. 12 is a flowchart of a method of performing serial point-to-pointinterconnection.

FIG. 13 is a flowchart illustrating a method of an example protocol.

FIG. 14 is a diagram illustrating an example flow control mechanism fora serial interconnect system.

FIG. 15 is a diagram illustrating an example of NACK message and retryprocess on MSG channel.

FIG. 16 is a diagram illustrating an example of successful datatransmission.

FIG. 17 is a diagram illustrating an example of error and retry ondownlink data transmission.

FIG. 18 is a diagram illustrating an example of successful uplinkmessage transmission.

FIG. 19 is a diagram illustrating an example of error and retry onuplink message transmission.

FIG. 20 is a diagram illustrating an example of error and retry triggerby error on flow control message.

FIG. 21 is a diagram illustrating an example of the sequence for writetransactions.

FIG. 22 is a diagram illustrating an example of the sequence for readtransactions.

FIG. 23 is a flowchart of a method of handling received packet.

FIG. 24 is a flowchart of a method of checking error for receivedpacket.

FIG. 25 is a flowchart of a method of handling received request.

FIG. 26 illustrates an example timing diagram that can repeatperiodically in a one lane configuration.

FIG. 27 illustrates examples of byte striping enabled.

FIG. 28 illustrates a data packet format and a message packet format.

FIG. 29 illustrates an example data link layer and physical layertransmission at a single physical lane.

FIG. 30 illustrates an example data link layer and physical layertransmission at three physical lanes.

FIG. 31 illustrates an example state machine that can be used to trackthe status of a high-speed serial link.

FIG. 32 is an example state diagram showing example power states andpower state transitions.

FIG. 33 is a diagram illustrating an example of a master inter-devicelink PHY block and an example of a slave inter-device link PHY block.

FIG. 34 is a conceptual block diagram illustrating a pair of examplecontrollers.

FIG. 35 is an example high-speed serial transceiver with programmabledistributed data processing functionality.

FIG. 36 is an example high-speed serial link with programmabledistributed data processing functionality.

FIG. 37 is a diagram illustrating an example representation of a linkkernel.

FIG. 38 illustrates an example slave external loopback testing mode.

FIG. 39 illustrates an example slave internal loopback testing mode.

FIG. 40 illustrates an example master internal loopback testing mode.

FIG. 41 illustrates an example link-to-link loopback testing mode.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of various configurations and isnot intended to represent the only configurations in which the conceptsdescribed herein may be practiced. The detailed description includesspecific details for the purpose of providing a thorough understandingof various concepts. However, it will be apparent to those skilled inthe art that these concepts may be practiced without these specificdetails. In some instances, well-known structures and components areshown in block diagram form in order to avoid obscuring such concepts.

Several aspects of serial interconnect systems will now be presentedwith reference to various apparatuses and methods. These apparatuses andmethods will be described in the following detailed description andillustrated in the accompanying drawings by various blocks, components,circuits, processes, algorithms, etc. (collectively referred to as“elements”). These elements may be implemented using electronichardware, computer software, or any combination thereof. Whether suchelements are implemented as hardware or software depends upon theparticular application and design constraints imposed on the overallsystem.

In some embodiments, some elements, or portions of some elements, orsome combinations of elements may be implemented as a “processingsystem” that includes one or more processors, as will be appreciated byone skilled in the art in light of this disclosure. Examples ofprocessors include microprocessors, microcontrollers, graphicsprocessing units (GPUs), central processing units (CPUs), applicationprocessors, digital signal processors (DSPs), reduced instruction setcomputing (RISC) processors, systems on a chip (SoC), basebandprocessors, field programmable gate arrays (FPGAs), programmable logicdevices (PLDs), state machines, gated logic, discrete hardware circuits,and other suitable hardware configured to perform the variousfunctionality described throughout this disclosure. One or moreprocessors in the processing system may execute software. Software shallbe construed broadly to mean instructions, instruction sets, code, codesegments, program code, programs, subprograms, software components,applications, software applications, software packages, routines,subroutines, objects, executables, threads of execution, procedures,functions, etc., whether referred to as software, firmware, middleware,microcode, hardware description language, or otherwise.

Accordingly, in one or more example embodiments, the functions describedmay be implemented in hardware, software, or any combination thereof. Ifimplemented in software, the functions may be stored on or encoded asone or more instructions or code on a computer-readable medium.Computer-readable media includes computer storage media. Storage mediamay be any available media that can be accessed by a computer. By way ofexample, and not limitation, such computer-readable media can comprise arandom-access memory (RAM), a read-only memory (ROM), an electricallyerasable programmable ROM (EEPROM), optical disk storage, magnetic diskstorage, other magnetic storage devices, combinations of theaforementioned types of computer-readable media, or any other mediumthat can be used to store computer executable code in the form ofinstructions or data structures that can be accessed by a computer.

FIG. 1 illustrates various aspects of the disclosure in an exampleimplementation of a cell phone 100. Cell phone 100 can include userinput components, such as a touchscreen 102, a button 104, etc. Insidecellphone 100 is a backplane 106, which is illustrated FIG. 1 in amagnified view to show details. Backplane 106 can be, for example, aprinted circuit board on which various components are attached. Forexample, a central processing unit (CPU) 108 and memory 110 can beattached to backplane 106. CPU 108 can be responsible for generalprocessing tasks of cell phone 100, such as displaying graphical userinterfaces on touchscreen 102, processing user input from thetouchscreen and button 104, running an operating system, etc.Specialized tasks can be performed by other components, such asapplication-specific integrated circuits (ASICs) 112 a-d. For example,ASICs 112 a-d can include a GPS ASIC to process GPS information, a touchASIC to process touch-sensing data, etc. CPU 108 and ASICS 112 a-d cancommunicate with each other through a bus 114.

The task of handling RF transmission and reception can be performed byan RFIC 118 and a BBIC 120. RFIC 118 and BBIC 120 can communicate witheach other through signal lines 122, which can be, for example, metaltraces on backplane 106. RFIC 118 can be connected to antennas 124 toprocess RF signals received by the antennas into downlink data and toprocess uplink data into RF signals to be transmitted by the antennas.BBIC 120 can be connected to bus 114 to communicate with the othersystems on backplane 106 in order to, for example, route downlink datato the appropriate system, prioritize and schedule uplink data to betransmitted, etc.

FIG. 1 includes a magnified view of RFIC 118 and BBIC 120. RFIC 118 caninclude a physical layer (PHY) component (referred to herein simply as a“PHY”), such as a PHY 130, a data link layer (DLL) component (referredto herein simply as a “DLL”), such as a DLL 132, a packet interface(PKTIF) 134, an analog-to-digital/digital-to-analog (ADC/DAC) converter136, and an RF section 138. RF section 138 can be connected to antennas124. In other embodiments, antennas can be integral with the RF section.BBIC 120 can include a PHY 140, a DLL 142, and interconnect bridges 144.The magnified view shows signal lines 122 can include one or more uplink(UL) signal lines 150 and one or more downlink (DL) signal lines 152.

For downlink communication, i.e., cell phone 100 receiving communicationfrom external sources such as cell towers, GPS satellites, etc., RFsection 138 can process analog RF signals received through the antennas(downlink signals), and ADC/DAC converter 136 can convert the processedanalog downlink signals into digital downlink signals. Packet interface134 can packetize the digital downlink signals into data packets.Packetization is a way to provide data with protection, identification,routing information, etc., in a computerized communication environment.For example, a header can be included in the data packet to indicate adestination address, a cyclic redundancy check (CRC) can be added to thedata packet to provide protection against errors during transmission,etc. Packet interface 134 packetizes the downlink signals according to acommunication protocol used by interconnect bridges 144 for transmissionof data over bus 114. This communication protocol is used by all of thecomponents attached to backplane 106 to communicate over bus 114.However, before the data packets from packet interface 134 can reachinterconnect bridges 144 and be transmitted over bus 114, the datapackets must be transmitted from RFIC 118 to BBIC 120 over downlinksignal lines 152.

Communication across downlink signal lines 152 can be governed by adifferent protocol, i.e., a serial link protocol. DLL 132 and PHY 130can further packetize the downlink data according to the serial linkprotocol. PHY 130 can transmit the further-packetized data acrossdownlink signal lines 152. PHY 140 can receive the further-packetizeddata, PHY 140 and DLL 142 can de-packetize the data packets, andinterconnect bridges 144 can transmit the data packets over bus 114.

Similarly, for uplink communications, i.e., cell phone 100 transmittingcommunication to external sources, interconnect bridges 144 can receiveuplink data packets through bus 114. DLL 142 and PHY 140 can furtherpacketize the uplink data packets according to the serial link protocol,and PHY 140 can transmit them across uplink signal lines 150. PHY 130can receive the uplink data packets, and PHY 130 and DLL 132 cande-packetize the data packets. Packet interface 134 can furtherde-packetize the uplink data packets into uplink signals so that thesignals can be properly transmitted by RF section 138. ADC/DAC converter136 can receive uplink signals from packet interface 134, convert thesedigital signals into analog signals, and send the analog uplink signalsto RF section 138 to be transmitted. RF section 138 can process analogRF signals to be transmitted through antennas 124.

According to certain aspects disclosed herein, an advanced digitalserial interface is provided. The digital serial interface can beimplemented, for example, between baseband and RF integrated circuits inmobile communication devices and the like.

In various embodiments, the digital serial interface may transmit andreceive based on a unidirectional clock signal between physical layers,such as PHY 130 and PHY 140 above. Unidirectional clock signaling can,for example, help to reduce the power consumption of the serial link.Examples of various aspects of unidirectional clock signaling aredescribed below with reference to FIGS. 2-5.

In various embodiments, the digital serial interface may include aserial link protocol that is engineered to optimize RF and basebandfunctions to provide high-speed, low-power serial link communication.Examples of various aspects of such serial link protocols are describedbelow with reference to FIGS. 8-12.

Furthermore, various embodiments can include a programmable distributeddata processor in the physical layer of a serial link, such as PHY 130and/or PHY 140 above. A programmable distributed data processor can addflexibility, while maintaining low-power operation, to otherwise fixedlink architecture. Examples of various aspects of such programmabledistributed data processors are described below with reference to FIGS.33-37.

Furthermore, various embodiments can include embedded functionality fortesting the serial link. In some embodiments, the embedded testing canbe performed in part by the programmable distributed data processor.Examples of various aspects of embedded testing are described below withreference to FIGS. 38-41.

FIG. 2 illustrates an example of a transceiver apparatus 200 thattransmits and receives signals across a high-speed serial link based onunidirectional clock signaling. In this way, for example, powerconsumption of the clock signaling circuitry can be lower compared tousing two clocks. The unidirectional clock signal can be used forsynchronization of the communication between a master and a slave overthe serial link. In this regard, transceiver apparatus 200 can include alink slave 202 and a link master 204. Link master 204 sends a clocksignal (CLK) 205 to link slave 202, and communication between the linkmaster and link slave over the high-speed serial link is based on CLK205. However, link slave 202 does not send a clock signal that is usedfor communication over the high-speed serial link to link master 204.This is an example of unidirectional clock signaling.

As used herein, unidirectional clock signaling is defined by one side ofa serial link sending a clock signal to the other side of the seriallink, where communication over the serial link is based on the clocksignal, and the other side not sending a clock signal on whichcommunication across the serial link is based. Also, as used herein, theterm “unidirectional clock signal” refers to the clock signal that issent in unidirectional clock signaling.

Transceiver apparatus 200 can include an RF section 206. RF section 206may include various circuitry related to the transmission and receptionof RF signals. For example, RF section 106 may include one or moreantennas. Additionally, RF section 206 may include one or more RFfilters or other RF processing circuits. Transceiver apparatus 200 canalso include an ADC/DAC 208, which may be used to convert received RFsignals (analog) from RF section 206 to digital signals in the ADCportion of ADC/DAC 208. For example, RF signals may be received at anantenna in RF section 206. The received RF signals may be filtered orotherwise processed in RF section 206.

The received RF signals (after any RF processing such as filtering thatoccurs in RF section 206) may then be converted to digital signals usingthe ADC in ADC/DAC 208. As illustrated in FIG. 2, in some examples, theRF signals may be converted from RF signals to digital signals orconverted from digital signals to RF signals directly, rather than atbaseband. The digital version of the received RF signals may then beprocessed digitally using the rest of the transceiver apparatus 200.

ADC/DAC 208 may also convert digital signals to analog signals in theDAC portion of the ADC/DAC. For example, digital signals received byADC/DAC 208 from a packet interface (PKTIF) 210 may be converted to RFsignals (analog) using the DAC portion of the ADC/DAC. The RF version ofthe digital signals received by ADC/DAC 208 from PKTIF 210 may then beprocessed as RF by filtering or other RF processing. The RF version ofthe digital signals received by ADC/DAC 208 from PKTIF 210 may betransmitted using the one or more antennas of RF section 206.

FIG. 2 illustrates various signals that can be transmitted between linkslave 202 and ADC/DAC 208. For example, digital signals that are toultimately be transmitted using the antenna or antennas of RF section206 may be sent from PKTIF 210 using the transmit front end (TxFE)signals illustrated in FIG. 2. Digital signals that are to be furtherprocessed by the rest of the transceiver apparatus 200 may be send fromADC/DAC 208 to PKTIF 210 using the receive front end (RxFE) signalsillustrated in FIG. 2. ADC/DAC 208 may provide feedback to PKTIF 210 viathe feedback receiver (FBRx) signal illustrated in FIG. 2. Incommunications systems that include position/location functionality,ADC/DAC 208 may also provide global navigation satellite system signals(GNSS) to the rest of transceiver apparatus 200 using the GNSS signalillustrated in FIG. 2.

PKTIF 210 can be coupled to a DLL 212, and DLL 212 can provide the PKTIFwith access to uplink data. Conversely, DLL 212 can provide access todownlink data to a link physical coding sublayer (PCS) 214. In thisregard, link PCS 214 may be a link protocol sublayer that resides on topof a serializer-deserializer (SERDES) transceiver 216 to provide aninterface between DLL 212 and SERDES transceiver 216. Together, PCS 214and SERDES transceiver 216 make up a PHY 217 of link slave 202.

SERDES transceiver 216 can receive downlink data from link PCS 214,serialize the downlink data, and transmit the serial downlink data to aSERDES transceiver 218 of link master 204 via downlink signal lines 219.SERDES transceiver 216 can also receive serial uplink data from SERDEStransceiver 218 via an uplink signal line 220, can deserialize theuplink data, and can send the deserialized uplink data to link PCS 214.As described above, this high-speed serial communication between linkmaster 204 and link slave 202 can be based on unidirectional clocksignaling. In this example, link master 204 can provide clock signal 205to link slave 202 via the serial link between SERDES transceivers 218and 216. In some embodiments, a clock signal from a link master to alink slave can be provided via other channels, such as a side-bandcommunication.

SERDES transceiver 218 can be coupled to a link PCS 221. Similar to linkPCS 214, link PCS 221 can be a link protocol sublayer that resides ontop of SERDES transceiver 218 to provide an interface between SERDEStransceiver 218 and a DLL 222 of link master 204. Together, PCS 221 andSERDES transceiver 218 make up a PHY 223 of link slave 202. DLL 222 canprovide downlink data to interconnect bridges 224, and the interconnectbridges can provide uplink data to DLL 222. Interconnect bridges 224 canbe connected to other devices, from which UL data may be received and towhich DL data may be sent. In various embodiments, unidirectional clocksignaling can provide several advantages. For example, reducing thenumber of components by eliminating one or more clocks can reduce thepin count and ports required, which can in turn reduce the number ofwires required on a printed circuit board on which the device resides.Fewer components also can reduce the IC area and lower the noiseenvironment. In various embodiments, unidirectional clock signaling mayhelp reduce the power required for operation of a high-speed seriallink.

Transceiver apparatus 200 can also include other power-savingfunctionality. For example, link master 204 can initiate a low-powermode in which the link master and link slave 202 enter a low-powerstate. In the low-power state, SERDES transceivers 216 and 218 do nottransmit. When the link slave 202 needs to wake up link master 204, thelink slave may use a link request (link_req) signal 226 that can betransmitted to the link master via a side-band (i.e. not via the seriallink between SERDES 216 and 218). Likewise, link master 204 may use alink enable (link_en) signal 228 (which may be an active low signal) toenable the inter-device link slave 202 to resume serial linkcommunication.

FIG. 3 illustrates an example SERDES transceiver configuration for aserial interconnect 300 that communicates high-speed serial data basedon unidirectional clock signaling according to various embodiments.Serial interconnect 300 can include a SERDES transceiver that acts as aslave 302 and a SERDES transceiver that acts as a master 304. Forexample, in some embodiments, SERDES transceivers 216 and 218 of FIG. 2can operate, respectively, as slave 302 and master 304.

In some applications, bandwidth requirements are not symmetrical. Inother words, a higher bandwidth may be required for data flowing in onedirection versus data flowing in the other direction. For example, cellphone users typically download much more data than they upload.Therefore, the downlink data bandwidth use is typically much higher thanuplink bandwidth use in cellular communication systems. In thesesituations, more downlink bandwidth versus uplink bandwidth can beprovided by, for example, using 3 DL lanes 310, 312, 314 and 1 UL lane316. Each lane can perform serial-to-parallel (S2P) conversion of data,parallel-to-serial (P2S) conversion of data, clock recovery, andassociated functions. Furthermore, each lane can use a common block thatgenerates clocks, bias and start-up sequences.

A lane is composed of one differential signaling pair, either for ULtraffic or for DL traffic. Thus, each lane is composed of two wires,signal traces, conductive pathways, etc. For example, DL lane 310includes two wires 340 and 342. DL lane 310 also includes a transmitter330 and a P2S component 334 at the slave 302, and a receiver 332, a S2Pcomponent 336, and a clock/data recovery (CDR) component 338 at themaster 304. Transmitter 330 sends information to receiver 332 throughthe two wires 340 and 342. P2S component 334 converts information fromparallel to serial format in order to be transmitted serially bytransmitter 330. S2P component 336 converts serial information receivedby receiver 332 into parallel format for further processing. CDRcomponent 338 performs clock/data recovery.

Serial interconnect 300 may be configured to generate a data link layerpacket for transmission of information to a second device. Generating adata link layer packet for transmission of information to a seconddevice may include performing an operation described below withreference to 1202 of FIG. 12. Generating a data link layer packet fortransmission of information to a second device may be performed by aprocessor associated with the master 304 or the slave 302.

The serial interconnect 300 may be configured to encapsulate the datalink layer packet within one or more physical layer frames.Encapsulating the data link layer packet within one or more physicallayer frames may include performing an operation described below withreference to 1204 of FIG. 12. Encapsulating the data link layer packetwithin one or more physical layer frames may be performed by a processorassociated with the master 304 or the slave 302.

The serial interconnect 300 may be configured to transmit the one ormore physical layer frames to the second device. Transmitting the one ormore physical layer frames to the second device may be performed in anoperation described below with reference to 1206 of FIG. 12.Transmitting the one or more physical layer frames to the second devicemay be performed by a P2S component (e.g., 334), a transmitter (e.g.,330), or wires (e.g., 340 and 342).

The serial interconnect 300 may be configured to receive a clock signalfrom the second device. Receiving a clock signal from the second devicemay be performed by the slave clock block 322 or the clock receiver 350.Transmitting the one or more physical layer frames may include operatingbased on the clock signal. Transmitting may further include refrainingfrom transmission of the clock signal to the second device.

The serial interconnect 300 may be configured to send a clock signal tothe second device. Sending a clock signal to the second device may beperformed by the master clock block 320 or the clock driver 352.Transmitting the one or more physical layer frames may include operatingbased on the clock signal.

The serial interconnect 300 may be configured to refrain from receivingthe clock signal from the second device. Refraining from receiving theclock signal from the second device may be performed by the master clockblock 320 or the clock driver 352.

The serial interconnect 300 may be configured to receive at least onephysical layer frame from the second device. Receiving at least onephysical layer frame from the second device may include performing anoperation described below with reference to 1208 of FIG. 12. Receivingat least one physical layer frame from the second device may beperformed by a S2P component (e.g., 336), a receiver (e.g., 332), a CDR(e.g., 338), or wires (e.g., 340 and 342).

The serial interconnect 300 may be configured to obtain one or more datalink layer packets based on the at least one physical layer frame.Obtaining one or more data link layer packets based on the at least onephysical layer frame may include performing an operation described belowwith reference to 1210 of FIG. 12. Obtaining one or more data link layerpackets based on the at least one physical layer frame may be performedby a processor associated with the master 304 or the slave 302.

The serial interconnect 300 may be configured to extract data ormessages based on the one or more data link layer packets. Extractingdata or messages based on the one or more data link layer packets mayinclude performing an operation described below with reference to 1212of FIG. 12. Extracting data or messages based on the one or more datalink layer packets may be performed by a processor associated with themaster 304 or the slave 302.

The asymmetry is introduced with the clock block. To improve therobustness of the solution, the serial interconnect 300 has synchronousoperation the master SERDES 304 providing the Clock to the slave SERDES302.

Each transmitter serializes a 20-bit parallel interface. This is drivenout with an h-bridge driver that has programmable swing levels. Thereceiver has access to linear equalization. The design provides amaximum bit rate of 6 Gbps.

The SERDES of the serial interconnect 300 can support the followingfunctions depending on the power, performance, and standard required:programmable Tx amplitudes; multiple TX and Rx termination settings;multiple power states; signal detection; extensive built-in testing,programmable CDR on and off times; multiple Calibrated phase lock loop(PLL) settings for fast frequency switching; multi-pattern BISTgeneration and BIST checking; multiplexed scan for testing of digitalcircuitry; multiple loopbacks; control register bus; direct currentjoint text action group (DC JTAG); on-chip jitter testing in associationwith frequency variation in parts-per-million (PPM), inter-symbolinterference (ISI), and bounded uncorrelated jitter (BUJ); 20 bitparallel interfaces for Rx and Tx.

Some of the specifications of the SERDES of the serial interconnect 300are bit error rate (BER) of 1e-16 or better (to achieve this BERspecification special attention can be taken for the board layout, e.g.,up to 6 inches can be the maximum length of the trace from/to RFICto/from BBIC, and shape of the trace can remain simple, e.g., curves canbe tolerated but sharp angles, via, connectors should be minimized), alllanes can be used at 6 Gbps with clock buffers running at 3 GHz infunctional mode.

Clock block 320 in master SERDES 304 acts as the clock transmitter inthis unidirectional clock signaling example and takes the clock providedby the PLL (high speed mode, functional) or an internal clock providedby the IC (low speed mode) and generates the needed intermediate clocksand sends the intermediate clocks to all the RX and TX blocks in themaster SERDES along with sending, via a clock driver 352, a half rateclock to the slave 302.

Clock block 322 in slave SERDES 302 acts as the clock receiver in thisunidirectional clock signaling example and receives, via a clockreceiver 350, the clock provided by master 304, generates the neededintermediate clocks and sends the intermediate clocks to all the RX andTX blocks in slave SERDES 302. A slow clock mode (low speed mode) isprovided to support slow speed operation. This mode can be used, forexample, in production test to accommodate the limit of testers. Due tothe high speed signals handle by the SERDES, calibration, terminationsetup can be needed for the Tx and Rx buffers.

For the purpose of illustrating a benefit of unidirectional clocksignaling, FIG. 3 also shows some components 399 that are not needed incomparison to conventional, bi-directional clock signaling (components399 are drawn with dashed lines to indicate the components are absentfrom the present design). In particular, unidirectional clock signalingcan allow elimination of a PLL and a clock driver on the slave SERDESside and a clock receiver on the master SERDES side. The elimination ofcomponents 399 can result in power savings because all of thesecomponents require power to operate. In addition, elimination ofcomponents 399 can reduce the chip area of serial interconnect 300,allowing the serial interconnect to be smaller. Finally, elimination ofcomponents 399 can reduce the number of pins, number of ports, andnumber of wires required to connect serial interconnect 300.

FIG. 4 is a flowchart of an example method of a master connected to aserial link, such as master SERDES 304 of FIG. 3, for performingunidirectional clock signaling according to various embodiments. Themaster can generate (401) a unidirectional clock signal based on a firstclock, in which the first clock is a clock in the master. For example,master SERDES 304 can generate a unidirectional clock signal based onmaster clock block 320. In some embodiments, the master may generate aunidirectional clock signal that is at the same rate as the first clock.In some embodiments, the master may generate a unidirectional clocksignal that is a fraction of the rate of the first clock, e.g., halfrate. The master can send (402) the unidirectional clock signal to aslave device that is connected to the serial link. For example, masterSERDES 304 can transmit the unidirectional clock signal via clock driver352. In some embodiments, the master can send the unidirectional clocksignal over the serial link to the slave. In some embodiments, themaster can send the unidirectional clock signal via another channel,such as a sideband, to the slave. The master can transmit (403) data tothe slave device over the serial link based on the first clock. Forexample, master SERDES 304 can transmit data to link slave SERDES 302over UL lane 316 based on master clock block 320.

In some embodiments, means for generating a unidirectional clock signalcan include the first clock and a programmable distributed dataprocessor, described in more detail below with reference to FIGS. 33-37.In other embodiments, means for generating a unidirectional clock signalcan include the first clock and a fixed state machine that controlsclock signaling of the link.

In some embodiments, means for sending the unidirectional clock signalcan include a SERDES transceiver, such as SERDES transceiver 218. Inother embodiments, means for sending the unidirectional clock signal caninclude a clock driver, such as clock driver 352.

In some embodiments, means for transmitting data to the slave deviceover the serial link can include a SERDES transceiver, such as SERDEStransceiver 218.

FIG. 5 is a flowchart of an example method of a slave connected to aserial link, such as slave SERDES 302 of FIG. 3, for performingunidirectional clock signaling according to various embodiments. Theslave can receive (501) a unidirectional clock signal from a master thatis connected to the serial link. For example, slave SERDES 302 canreceive a unidirectional clock signal via clock receiver 350 from masterSERDES 304. In some embodiments, the unidirectional clock signal can bereceived over the serial link. In some embodiments, the unidirectionalclock signal can be received via another channel, such as a sideband.The slave can transmit (502) data over the serial link to the masterbased on the unidirectional clock signal. For example, slave SERDES 302can transmit data over DL lane 310 to master SERDES 304. In someembodiments, the slave can set an internal clock based on theunidirectional clock signal, and transmission of data over the seriallink can be based on this internal clock.

It should be noted that the logical sub-block (e.g., PCS) of a physicallayer can provide a means for interfacing between the DLL and theelectrical sub-block (e.g., SERDES transceiver block) and can providemechanisms to further encapsulate a data link layer packet beforesending the encapsulated DLL packet to the electrical sub-block fortransport (e.g., over signal lines). The logical sub-block can multiplexpacket information that is multiplexed, striped across all availablelanes and scrambled before being packaged into frames (e.g., 130-bitframes).

The logical sub-block can have two main sections: a transmit sectionthat prepares outgoing information passed from the Data Link Layer fortransmission by the electrical sub-block; and a receiver section thatidentifies and prepares received information before passing the receivedinformation to the Data Link Layer. The logical sub-block and electricalsub-block can coordinate the state of each transceiver through a statusand control register interface or functional equivalent.

The physical layer of the serial interconnect can use a 128b/130bencoding scheme, which can limit the overhead to 1.5% per data frame(versus, for example, the 20% overhead required by using 8b/10bencoding). The frame size is 130 unit intervals (UIs). Each UI containsone bit of information. Out of the 130 bits, 2 bits carry a framesynchronization symbol, and the remaining 128 bits carry data symbols(i.e., 128b/130b encoding). A UI can be a constant time interval fortransmission of 1 bit of information (The UI is the inverse of the bitrate. At 6 Gbps, 1 UI=0.16 ns). A frame can be 130 bits (1 frame can betransmitted in 130 UIs in a single lane, and the frame can contain 128bits of information and 2 bit synchronization symbol). A block can be130 bits multiplied by the number of bits per lane (1 block can betransmitted in 130 UIs (after deskew), and the block can contain 128bits of information and 2 bit synchronization symbol per lane). Asynchronization symbol can be 2 bits (the synchronization symbol can betransmitted periodically at the start of each Physical Layer frame, andthe synchronization symbol can be used to differentiate between PhysicalLayer messaging and data link layer messaging, e.g., 01 can identify apacket burst frame (Data link layer communication), and 10 can identifya PHY burst frame (Physical Layer communication)).

In some embodiments, means for receiving a unidirectional clock signalfrom a master that is connected to the serial link can include a SERDEStransceiver, such as SERDES transceiver 216. In other embodiments, meansfor receiving a unidirectional clock signal from a master that isconnected to the serial link can include a clock receiver, such as clockreceiver 350.

In some embodiments, means for transmitting data over the serial link tothe master based on the unidirectional clock signal can include a SERDEStransceiver, such as SERDES transceiver 216.

FIG. 6 is a diagram illustrating an example operation 600 performed overa serial interconnect system 602. The serial interconnect system 602may, for example, provide a low-latency mechanism for a BBIC to accessan RFIC memory and registers. A BBIC master 606 may write up to 1024bits of data to successive RFIC control/status registers (CSRs) 612.Similarly, a BBIC master 606 may request a read transfer of up to 1024bits of successive RFIC CSR locations 612. All RFIC 604 initiated readand write transfers transferred across the serial interconnect system602 using a credit based flow-control mechanism that ensures reliabletransfers.

The serial interconnect system 602 provides a full-duplex interface(uplink and downlink) between RFIC 604 and BBIC 606 in a modem system.The protocol of the serial interconnect system 602 defines the transportof data and control information in a packetized format. A controller ofthe serial interconnect system 602 implements the protocol. The SERDESof the serial interconnect system 602 provides a high-speed serialtransport mechanism.

Serial data are transported over one or more lane in uplink and downlinkdirections. All data lanes operate synchronously and share the samenominal bandwidth. Synchronization between transmitter and receiver sideof the serial link is ensured by a shared clock 608 that is sent fromthe BBIC 606 to the RFIC 604. Using a unidirectional clock signal canreduce the power for transmission and reception of data over the seriallink, for example, because one fewer PLL is needed. Using aunidirectional clock signal can also reduce the number of pins requiredfor the device.

In a typical baseband, downlink data traffic requires more bandwidththan uplink data traffic. Since bandwidth scales linearly with thenumber of lanes, the bandwidth requirement may be met by providing morethan one data lanes.

Downlink data traffic represents data samples received from an antenna,converted by an ADC in the RFIC 604, filtered, down-sampled and sent tothe BBIC 606 over the serial interconnect system 602. Multipleindependent data paths 614 exist, namely aggregated carriers withinreceiver front end (RXFE) and global navigation satellite system (GNSS).Uplink data traffic goes through the transmitter front end (TXFE) datapath, which has an overall lower bandwidth requirement than theaggregate downlink data paths. The serial interconnect system 602 isconcerned only with the source and the destination of the data soingress and egress data buffers are external to the serial interconnectsystem 602. All data is presented to the serial interconnect system 602via a uniform interface. The data traffic is real-time traffic.

In addition to data traffic, the serial interconnect system 602 alsosupports control traffic, which comprises accessing memory and CSRlocations on the RFIC 604. While control traffic is given priority overthe data traffic, control access to RFIC CSRs 612 is not guaranteedfixed latency.

In addition to data and control traffic, the serial interconnect system602 also provides a link-layer messaging mechanism for exchangingflow-control and interrupt messages. Messages in the serial interconnectsystem 602 are not directly accessible by upper layers and are consumedin their entirety by the data link layer of the serial interconnectsystem 602.

FIG. 7 is a diagram illustrating an example of a high-bandwidth,low-latency serial interconnect system 702 optimized for a modemchipset, especially for communication between a BBIC and an RFIC. Theserial interconnect system 702 is optimized for low cost, low power andlow bit error rate. The main purpose of the serial interconnect system702 is to transfer data across the link, including uplink (UL) 710 anddownlink (DL) 708 between the BBIC 706 and the RFIC 704. The data sourceand destination points are presented to the serial interconnect system702 as FIFO interfaces 712. The serial interconnect system 702 isresponsible for ensuring reliable exchange of data across the link usingtoken-based flow control mechanisms and retries.

A serial link protocol that is engineered to optimize RF and basebandfunctions to provide high-speed, low-power serial link communicationwill now be described with reference to FIGS. 8-12.

FIG. 8 is a diagram illustrating a layered model that implements aserial interconnect system 800. The serial interconnect system 800 maybe, for example, serial links described above with reference to FIGS. 1and 2. The serial interconnect system 800 uses packets to communicateinformation between layers. Packets are formed in the packetizationlayer 802 to carry the information from the data source in thetransmitter (Tx) component 810, or to the data sink in the receiver (Rx)component 812. As the transmitted packets flow through the link layer804 and physical layer 806, the packets are encapsulated with additionalinformation necessary to handle packets at those layers. At thereceiving side, the reverse process occurs, and packets get transformedfrom their physical layer 806 and link layer 804 representation to theform that can be processed by the packetization layer 802 of thereceiving device.

The packetization layer 802 is responsible for the following functions:converting between an I/Q stream and fixed-length packet stream for eachlogical end-point; managing the source/destination address for eachUL/DL packet; and issuing read/write requests associated with each UL/DLpacket. The DLL 804 is responsible for the following functions: adding apacket header; adding redundant bits for CRC; tracking the flow controlcredits for packets across the serial link; managing packetacknowledgment (ACK) and retry messages; error checking, error handling,error reporting of DLL packet errors; and handling power statetransitions.

The PHY 806 is divided into two sub-blocks: the logical sub-block 814and the electrical sub-block 816, aka SERDES. The PHY logical sub-block814 is responsible for the following functions: packing/unpacking DLLpackets into blocks and frames; insertion of equalization andsynchronization bursts for the SERDES; adding physical layer framingtokens to the DLL packet stream; scrambling and descrambling of DLLpackets and PING PHY burst; enforcing PHY layer framing rules at thereceiver; and framing and alignment of received bit stream. The SERDES816 is responsible for the following functions: converting parallel datainto serial data at the transmitting device; and converting serial datainto parallel data at the receiving device.

In one configuration, the serial interconnect system 800 includes aserial interface with a maximum of 6 Gbps raw bandwidth per lane. Theoutput frequency of PLL may be programmable. Source-synchronous clockmay be used for all UL and DL lanes in serial interconnect system 800.Master SERDES has PLL, and forwards clock to slave SERDES. The serialinterconnect system 800 may include a double data rate (DDR) clock. TheDDR clock may be Up to a maximum of 3 GHz clock for 6 Gbps data rate.The serial interconnect system 800 may include spread-spectrum control(SSC) support (e.g., center-spread or down-spread) for RFde-sensitization. The serial interconnect system 800 includespower-saving states during idle periods. The power states of the serialinterconnect system 800 may range from light sleep to deep sleepproviding different levels of power/exit latency trade-offs.

In one configuration, the PCS of the serial interconnect system 800 mayuse 128b/130b encoding scheme, which has lower overhead encoding than8b/10b encoding used by traditional serial interconnect systems. Theserial interconnect system 800 uses 2 bits synchronization symbols,which minimize framing synchronization symbols to determine packetboundaries.

In one configuration, the serial interconnect system 800 uses simple androbust messaging (e.g., patterns defined for link training, scrambleroperation, transitions to low-power state, etc.) upon entry and exit ofpower-saving states. The serial interconnect system 800 may employmulti-lane operation. The serial interconnect system 800 may use lanestriping, in which data is sent across all available lanes for optimalbandwidth utilization and robustness against burst errors in packetburst mode.

In one configuration, packet header may contain channel identification(ID), which is protected by CRC. Error detection of the serialinterconnect system eliminates risk of packet routing to wrongdestination, and triggers retry mechanism. Link ID specifies routinginformation for each endpoint.

Multiple link IDs may be allocated for data samples and CSR accesses.The serial interconnect system 800 may include side band communication,e.g., one side band signal in each direction to provide a mechanism forreset/wake and error recovery. The serial interconnect system 800 mayinclude ping mode. Ping operation separates bit error rate (BER)profiling at the PHY and DLL layer.

The DLL is responsible for reliably transporting message and datapackets across the serial link. The DLL may perform data exchange. Forexample, the DLL may accept packets for transmission and convey them tophysical layer. The DLL may also accept packets received over physicallayer and convey the packets to the destination. The DLL may performerror detection and retry. For example, the DLL may perform packetsequence number management for all DLL packets. The DLL may also add CRCprotection for all DLL packets. The DLL may perform data integritychecking for packets. For example, the DLL may generate positive andnegative acknowledgement. The DLL may also generate error indicationsfor error reporting and logging mechanisms.

The serial interconnect system 800 may include two types of DLL packets:data packet or message packet. Data packet may be used for datatransfers as well reads and writes to RFIC CSRs. Message packet maycontain messages exchanged between DLL layers across the serial link.Message packet may be used for event signaling and flow-controlmessaging.

Examples of DL traffic (from slave) in the serial interconnect system800 may include RFIC slave write request transactions specifying thedestination address, write-data (maximum of 1024 bits) and length indouble-words, read response data corresponding to a previous BBIC readrequest (on UL sublink), messages from RFIC DLL entity to BBIC DLLentity for events (EVT) messages for BBIC, RFIC read requests (RD_REQ)messages specifying the source address and length in double-words, andflow control messages to BBIC DLL entity. Examples of UL traffic (toslave) in the serial interconnect system 800 may include, read responsedata corresponding to a read request (RD_REQ) message issued by the RFICon the DL sublink, BBIC write requests specifying the destinationaddress, write data (up to 1024 bits) and length in double-words,messages from BBIC DLL entity to RFIC DLL entity, such as events (EVT)messages for RFIC, and BBIC read request (RD_REQ) messages specifyingthe source address and length in double-words; EVT, and flow controlmessages to RFIC DLL entity.

All DLL transfers over the serial interconnect system 800 consists ofpackets.

FIG. 9 is a diagram illustrating example packet structures of two typesof fixed-length packets formed by a DLL of a serial link. The two typesof packets are a message (MSG) packet 910 (also referred to as a DLLcontrol packet) and a data packet 920.

MSG packet 910 has a fixed length of 56 bits, comprising a 24-bitheader, a 16-bit payload, and a 16-bit CRC. The payload of MSG packets910 can be used to control various aspects of the serial link, and thepayload can therefore be referred to as a control message. Once the DLLpacketizes the control message, the packetized control message can bereferred to as a DLL control packet (i.e., a control message packetizedat the DLL level).

Data packet 920 has a fixed length of 1080-bits, comprising a 24-bitheader, a 1024 bits payload, and a 16-bit CRC. In various embodiments,message and data packets can be independent and can be multiplexed onthe link for transmission, with priority given to the MSG packets. Thiscan allow high priority messages, such as events (EVT), to betransmitted with minimal delay.

An example packet format according to various embodiments is describedin Table 1 below:

TABLE 1 Packet Format Packet No. of Type Field Bit index bitsDescription MSG type [3:0] 4 Type for MSG: {RD_REQ, EVT, FC/ACK/NACK,Other} link_id/ [7:4] 4 Specifies the link_id for sub_type the RD_REQmessages; Specifies the 4 MSBs for the event number for EVT typemessages; Reserved for all other types seq_num [15:8]  8 SequenceNumber. Updated once for each outgoing message length/ [23:16] 8Specifies the read length in sub_type double-words for RD_REQ messages;Specifies the 8 LSBs of the event number for EVT type messages; Reservedfor all other types payload [39:24] 16 For RD_REQ types, the payloadcarries the 16-bit source address* (rd_addr); For EVT types, the payloadcarries 16-bits of event data; For all other types, this field carriesthe message payload CRC [55:40] 16 16-bit CRC DATA type [3:0] 4 Type for{WR_DATA, RD_RESP, Other} link_id [7:4] 4 Link One of up to 16 logicalend-points for the data link layer seq_num [15:8]  8 Sequence NumberLength [23:16] 8 Length in double-words for the transfer (number-1) of32 bits words to be transferred For one 32 bits word of data, Length = 0Addr [39:24] 16 Destination address of 32 bits Word payload [1063:40] 1024 Up to 1024 bits of payload CRC [1079:1064] 16 16-bit CRC

Each packet has a message section and a data section. The message anddata packets are protected by 16-bit CRC.

The different message types supported according to various embodimentsare described in Table 2 below:

TABLE 2 Message Type Encoding Value Description 4′b0001 Read Request(RD_REQ) 4′b0010 Event (EVT) 4′b0100 Other Message 4′b1111 Flow ControlMessage All others Reserved

The different data transfer types supported in accordance with variousembodiments are described in Table 3 below:

TABLE 3 Data types Value Description 4′b0001 Write Request (WR_REQ)packet 4′b0010 Read Response (RD_DATA) packet 4′b0100 Other DATA packetAll others Reserved

The different data/message sub-types supported in accordance withvarious embodiments are described in the table 4 below:

TABLE 4 Message sub-type Encoding Value Description 8′h00 ACK_MSG 8′h01ACK_DATA 8′h08 NACK_MSG 8′h09 NACK_DATA All others Reserved

The DLL layer defines up to 16 logical end points in each direction.Each end-point is allocated a fixed “link_id”. All packets associatedwith an end-point use this “link_id”. All data packets with link idsbetween 1 and 15 are treated as one class of bulk transfers. Datapackets with link_id set to zero are used for CSR reads and writes. CSRaccesses are given priority over the link compared to data packets fromother end-points. The different link identifiers supported in accordancewith various embodiments are described in the table 5 below:

TABLE 5 Link Identifiers Link_ID value UL Path DL Path 4′h0 Control, AHBR/W Control, AHB R/W 4′h1 TxFE-0 GNSS 4′h2 TxFE-1 RxFE-0 4′h3 ReservedRxFE-1 4′h4 Reserved RxFE-2 4′h5 Reserved RxFE-3 4′h6 Reserved RxFE-44′h7 Reserved RxFE-5 4′h8 Reserved RxFE-6 4′h9 Reserved RxFE-7 4′hAReserved RxFE-8 4′hB Reserved RxFE-9 4′hC Reserved FBRX 4′hD ReservedRefLog 4′hE Reserved Reserved 4′hF Sequencer communication Sequencercommunication

The DLL uses sequence numbers for flow control on each sublink. MSG andDATA packets use separate sequences number. Sequence numbers are addedto each packet by the transmitter and checked by the receiver.

FIG. 10 is a diagram illustrating an example packet burst structure atthe PHY in accordance with various embodiments. As shown, at the PHY,MSG packet 910 from the DLL can be further packetized by adding an 8-bitMPT token 1002 in front to create a MSG packet 1001, which can bereferred to as a PHY control packet. Thus, the total length of MSGpacket 1001 is 64 bits (i.e., 8-bit MPT token 1002 length plus 56-bitMSG packet 910 length).

Similarly, an 8-bit DPT token 1004 is placed in front of data packet 920(1080 bits) from the DLL to form an data packet 1003. Thus, the totalsize of data packet 1003 is 1088 bits.

FIG. 11 is diagram illustrating an example 128/130b encoding of messageand data packet at the physical layer with dual message framing inaccordance with various embodiments. In the 128b/130b encoding shown inFIG. 11, exactly two MSG packets 1001 can fit into a single 130-bit PHYframe 1101. In other words, an encapsulation length of the 128b/130bencoding is 128 bits, which is exactly twice the length of the PHYcontrol packet (i.e., MSG packet 1001). This dual message framing canhelp increase the efficiency of the message transmission. In particular,in a system in which messages are given a high priority, no more thantwo messages will be waiting in a queue for transmission slots at anygiven time.

As shown in FIG. 11, encoding at the physical layer includes forming aframe by adding a 2-bit packet burst synchronization symbol 1102 infront of a first MSG packet 1001 a, which is placed in front of a secondencapsulated MSG packet 1001 b to form 130-bit PHY frame 1101. PHY frame1101 can be sent immediately with all of the payload space filledbecause the two 64-bit MSG packets fit exactly into the 128-bitencapsulation length of the PHY frame.

FIG. 11 also shows a single data packet 1003 packetized into multiplePHY frames 1101 b-n, with data packet 1003 being divided into multipleportions and the portions inserted into the multiple, successive PHYframes 1101 b-n. As shown in FIG. 11, PHY frame 1101 b includessynchronization symbol 1102, along with the DPT, the data header, and aportion of the data payload of data packet 1003. Each of PHY frames 1101c-m includes synchronization symbol 1102 and a portion of the datapayload of data packet 1003. PHY frame 1101 n includes synchronizationsymbol 1102, along with the last portion of the data payload and the CRCof data packet 1003, which do not fill the entire 128 bit encapsulationlength of PHY frame 1101 n. Therefore, PHY frame 1101 n has additionalspace to fit more data or messages.

The serial interconnect system allows for byte striping (also known asdata interleaving) across multi-lane sublinks when in packet burst mode.Data transmitted on more than one lane is interleaved, meaning that eachbyte in the transfer is sent in successive lanes. This disclosure refersto this interleaving as byte striping. Striping requires additionalhardware complexity to deskew the incoming striped bytes, but stripingcan significantly reduce the latency in a manner proportional to thetransfer length of the packet burst and the number of lanes beingutilized for the data transfer.

FIG. 12 is a flowchart of a method of performing serial point-to-pointinterconnection. The method may be performed by a first device, such aslink slave 202 or link master 204 of FIG. 2. At 1202, the first devicegenerates a data link layer packet for transmission of information to asecond device. In one configuration, the DLL packet may be generated bylink layer 604 of FIG. 6 based on the packet structures described abovewith reference to FIG. 9.

At 1204, the first device encapsulates the data link layer packet withinone or more physical layer frames. In one configuration, a physicallayer frame may be generated by physical layer 606 of FIG. 6 based onthe structure described above with reference to FIG. 10. In oneconfiguration, each of the one or more physical layer frames includes asynchronization symbol. A ratio of the length of the synchronizationsymbol to the length of a physical layer frame may be less than 2 to 10.

At 1206, the first device transmits the one or more physical layerframes to the second device. For example, the first device can be linkslave 202 of FIG. 2 and the second device can be link master 204 of FIG.2. In such configuration, the first device receives a clock signal fromthe second device. For example, link slave 202 can receive clock signal205 from link master 204. The transmitting of the one or more physicallayer frames may be based on the clock signal. The clock signal isunidirectional. Thus, the first device refrains from transmission of aclock signal to the second device.

At 1208, the first device receives at least one physical layer framefrom the second device. At 1210, the first device obtains one or moredata link layer packets based on the at least one physical layer frame,for example, by processing in link layer 604 of FIG. 6. At 1212, thefirst device extracts data or messages based on the one or more datalink layer packets.

In one configuration, a data link layer packet is a data packet for datatransfers. The length of the data packet is 1080 bits and the datapacket includes a 24-bit header, a 1024 bits payload, and a 16-bit CRC.In one configuration, a data link layer packet is a message packet forevent signaling and flow-control messaging. The length of the messagepacket is 56 bits and the message packet includes a 24-bit header, a16-bit payload, and a 16-bit cyclic redundancy check (CRC).

In one configuration, all message packets may be streamed across asingle virtual message channel and all data packets may be streamed overa virtual data channel. In such configuration, the virtual messagechannel and the virtual data channel may use independent flow-controlmechanisms. The virtual message channel may employ implicitacknowledgment for flow control and the virtual data channel may employa credit based flow control.

In one configuration, each physical layer frame is 130 bits long andincludes a 2-bit synchronization symbol. The 2-bit synchronizationsymbol is outside of the data link layer packet. The 2-bitsynchronization symbol may indicate one of two operating modes for thephysical layer: a packet burst or a physical layer burst. The packetburst is used for data link layer communication between the first deviceand the second device. The physical layer burst is used for physicallayer communication. In one configuration, at least one physical layerframe may further include an 8-bit token, which differentiates packettypes for the packet burst and differentiates physical layercommunication types for the physical layer burst. In one configuration,the physical lane frames are transmitted or received over one or morephysical lanes.

FIG. 13 is a flowchart illustrating a method of an example protocol ofencoding message and data packet at the physical layer with dual messageframing in accordance with various embodiments. The method of FIG. 13could be performed, for example, by an RFIC or BBIC described above. Thedevice can generate (1301) DLL control packets for transmission ofcontrol messages to a second device. For example, the DLL controlpackets can be MSG packets 910 of FIG. 9. Each DLL control packet canhave a DLL control packet length, the DLL control packet length being afixed length. For example, the fixed length of MSG packet 910 is 56bits. The device generates (1302) PHY control packets. Each PHY controlpacket includes one of the DLL control packets and a control token. Thelength of each PHY control packet is the sum of the DLL control packetlength and a control token length of the control token. For example, thePHY control packet can be MSG packet 1001 of FIG. 10, which includes a56-bit MSG packet 910 and an 8-bit MPT token 1002 for a total length of64 bits. The device encapsulates (1303) the PHY control packets inframes. Each of the frames includes a synchronization symbol having asymbol length. The length of each frame is the sum of the symbol lengthand an encapsulation length, and the encapsulation length is twice thelength of the PHY control packet. For example, PHY frame 1101 includessynchronization symbol 1102 of 2 bits, and further includes two 64-bitMSG packets 1001 in an encapsulation length of 128 bits. The devicetransmits (1304) the frames to the second device. In some embodiments, aratio of the encapsulation length to the length of each frame is 64/65,for example, in the 128b/130b encoding described above.

In some embodiments, the synchronization symbol indicates one of twooperating modes for the PHY. The operating modes include a packet burstused for data link layer communication between the device and the seconddevice, and a physical layer burst used for physical layercommunication. In some embodiments, the DLL control packet length is 56bits, and the control token length is 8 bits.

In some embodiments, the device can further generate DLL data packetsfor transmission of data to the second device, where the data isobtained with a read request from a memory, the read request returning afixed data length of the data. Further more, each DLL data packet caninclude a data payload having a data payload length that is a multipleof the data length of the data returned by the read request. The devicecan generate PHY data packets, where each PHY data packet includes oneDLL data packet and a data token, and the device can encapsulate the PHYdata packets in the frames. In some embodiments, the data payload lengthis 1024 bits.

Means for generating DLL control packets for transmission of controlmessages to a second device can include a DLL, such as DLLs 212 and 222.

Means for generating physical layer (PHY) control packets can include aPHY, such as PHYs 217 and 223.

Means for encapsulating the PHY control packets in frames can include aPHY, such as PHYs 217 and 223.

In some embodiments, means for transmitting the frames to the seconddevice can include SERDES transceivers, such as SERDES transceivers 216and 218.

FIG. 14 is a diagram illustrating an example flow control mechanism fora serial interconnect system according to various embodiments. DATAtransfers 1420 implement a bulk acknowledge scheme, wherein an ACK MSG1422 is sent once the credit for the traffic class has been exhausted.The receiver also compares the sequence number of each DATA packet andsends a negative acknowledgment (NACK) message to the DLL if thereceiver detects an unexpected sequence number.

The acknowledgement policy for MSG packets 1410 is a little different.All MSG packets share a common sequence number. The receiver implicitlyacknowledges each MSG packet and sends a retry message only in the eventthat the receiver detects a sequence number error for MSG packets. Allmessages following the last correctly received MSG must be discarded bythe receiver and retried by the transmitter. The link layer control(LLC) can maintain a deep enough message buffer to cover the worst-caseround-trip delay between the transmitting and receiving DLL entities.

The serial interconnect system is a point-to-point communication channelbetween the RFIC and the BBIC. ACK messages are used for credit-basedflow control communication. Flow control occurs independently betweenMSG and DATA channels of the frame package. The message (MSG) and data(DATA) channels use independent flow-control mechanisms. All readrequests event messages, and other messages packets are arbitrated andstreamed across a single virtual message channel. All write requests andread response packets are arbitrated and streamed over the DATA virtualdata channel. The link id field is used to distinguish between data andCSR accesses. Grouping all data traffic into a single credit-ACK queueallows for more efficient buffer management and lower overhead of ACKresponses. Treating CSR accesses as a separate traffic class enableslow-latency transfers of control traffic across the serial link byavoiding head-of-line blockage due to data packets.

The serial interconnect system can use a credit based flow control tomake sure that before a packet can be sent across the link, thereceiving side has sufficient buffer space to accept the packet. Asdescribed earlier, the two sides of the interconnect exchanges MSG andDATA packets. MSG and DATA are independent, which must arbitrate fortransmit access over the serial link. The transmission credit isinitialized to a maximum value upon power-up or reset. The RFIC shalldecrease its DATA channel credit every time a data packet is transmittedfrom the RFIC to the BBIC. The BBIC will process the data packets andtransmit to the RFIC an ACK MSG periodically to acknowledge allcorrectly received DATA packets. Upon receiving an ACK message the RFICupdates its credit counter. A similar mechanism applies to CSR DATAchannel.

In contrast, MSG transfers 1410 do not necessarily employ a credit basedACK scheme. Instead, all MSG packets are assumed to be receivedcorrectly. NACK messages are sent whenever an unexpected MSG sequencenumber is found by the receiving DLL entity.

For robust exchange of data and control information, two mechanisms canbe built into DLL packet. Each DLL packet has 16-bit CRC, and the CRC ischecked against expected CRC once the packet is received. Also, both MSGand DATA portion carries an 8-bit Seq_num field, which is sequentiallyincremented and maintained independently on MSG and DATA channel whenpacket is assembled at transmitter side; and the receive side checksreceived MSG/DATA Seq_num to make sure that there are no dropped MSG orDATA. Whenever CRC error or out-of-order MSG/DATA Seq_num is detected,receive side shall report the error status to transmitter side. Uponreceiving this error report, the transmitter side will try re-sendMSG/DATA.

This error reporting and retry mechanism may require transmitter sideretain the buffer of MSG/DATA even after those MSG/DATA have been sent,just in case error occurs on the link and they were not successfullyreceived. On the other hand, receive side may report to transmitter sidewhen MSG/DATA are successfully received and pushed into iMSG/iDATAbuffer 1414/1424 so that transmitter side can release locations occupiedby those MSG/DATA and free up space on its eMSG/eDATA buffer 1412/1422.With sufficient eMSG and eDATA buffers on both sides of the serialinterconnect, and little push-back on popping of iMSG or iDATA bufferson both sides, flow control (FC) message may serve as a conservative andfrequent status report on correctly received MSG/DATA, and transmitterside may only need to retain contents between Credit_ptr and Wr_ptr.

Special message type NACK is defined for reporting error on receivedpacket and for request retry. An example definition of NACK message inaccordance with various embodiments is illustrated in Table 6:

TABLE 6 NACK message definition Bit No. of Field index bits Descriptiontype [3:0] 4 Type for MSG = 4′hF link_id [7:4] 4 link_id for MSG = 0seq_num [15:8]  8 seq_num for MSG = 0 (NACK message does not go intoeMSG buffer) payload [55:16] 39 Usage: [23:16] = MSG channel iMSG bufferWr_ptr pointed Seq_num, [24] = MSG channel iMSG buffer Wr_ptr pointedSeq_num valid (bit [23:16] valid) [39:32] = DATA channel iDATA bufferWr_ptr pointed Seq_num. [40] = DATA channel iDATA buffer Wr_ptr pointedSeq_num valid (bit[39:32] valid) [55:41] = reserved

To make sure NACK message is conveyed to the other side, each generatedNACK message may be subject to triple transmission protection:transmitter transmits the same NACK message three times; and receivermay combine and merge three consecutive NACK MSGs to form a retryaction. If CRC failed on any of the three NACK messages, the failedpayload will be thrown out and not used at the payload combining.

FIG. 15 is a diagram illustrating an example of NACK message and retryprocess on MSG channel according to various embodiments. NACK message onDATA channel is similarly handled. Note that once the remote DLL entitydetects an error on one received packet, later packets on the samechannel will not be pushed into iMSG/iDATA buffer until tripletransmission of the NACK message is done, and then the subsequentlyreceived MSG/DATA is correct and has sequential seq_num to the lastpushed in MSG/DATA.

In this example, the de-packetizer 1503 on the receiver side of theserial interconnect detects extracts a MSG whose seq_num is 4. An erroris detected on that that MSG. The receiver side then generates a NACKmessage to indicate the error on MSG with seq_num equals to 4. Uponreceiving the NACK message, the transmitter side rewind Rd_ptr to pointto MSG 4 for retry/retransmission.

The NACK/retry process described in FIG. 15 may protect essentialmessage and data exchanged by two sides of the serial interconnect.However, if error occurs on packet that contains FC message, there is noretry on FC messages since they are not pushed into eMSG buffer duringtransmission. To protect the mixed messages including FC messages, thefollowing protocol may be added: if one side detects error on a packet,and issues NACK message, while NACK message is being transmitted, theside still needs to process correctly received FC messages if any; whenthe opposite side receives the NACK message, the opposite side shallrespond by an immediate transmission of FC message. FIGS. 16-20 belowillustrate this NACK-FC-retry protocol.

FIG. 16 is a diagram illustrating an example of successful datatransmission in accordance with various embodiments. In this example,upon successful reception of data packets 0-3 at a BBIC 1604, the BBICsends a message packet 0 to an RFIC 1602. The message packet 0 indicatesthat the BBIC 1604 has received data packets 0-3 and the expectedseq_num of the next data packet to be received at the BBIC 1604 is 4.

FIG. 17 is a diagram illustrating an example of error and retry ondownlink data transmission in accordance with various embodiments. Inthis example, an RFIC 1702 sends data packets 6-10 to a BBIC 1704 insequence. During the transmission of data packet 7, a bit error (e.g.,CRC mismatch or unexpected seq_num) occurs. In response to the bit erroron data packet 7, the BBIC 1704 discards the received data packets 8-10and sends a NACK message to indicate the error on data packet 7. Uponreception of the NACK message at the RFIC 1702, the RFIC sends a FCmessage to the BBIC 1704. Subsequently, the RFIC 1702 re-sends datapackets 7-10 to the BBIC 1704.

FIG. 18 is a diagram illustrating an example of successful uplinkmessage transmission in accordance with various embodiments. In thisexample, upon successful reception of message packets 9 and 10 at anRFIC 1802, the RFIC sends a message packet 1 to a BBIC 1804. The messagepacket 1 indicates that the RFIC 1802 has received message packet up tosequence number 10 and the expected seq_num of the next message packetto be received at the RFIC 1802 is 11.

FIG. 19 is a diagram illustrating an example of error and retry onuplink message transmission in accordance with various embodiments. Inthis example, a BBIC 1904 sends message packets 9-11 to an RFIC 1902 insequence. During the transmission of message packet 10, a bit error(e.g., CRC mismatch or unexpected seq_num) occurs. In response to thebit error on message packet 10, the RFIC 1902 discards the receivedmessage packet 11 and sends a NACK message to indicate the error onmessage packet 10. Upon reception of the NACK message at the BBIC 1904,the BBIC sends a FC message to the RFIC 1902. Subsequently, the BBIC1904 re-sends message packets 10 and 11 to the RFIC 1902. Uponsuccessful reception of message packets 10 and 11 at the RFIC 1902, theRFIC sends a message packet n+1 to the BBIC 1904. The message packet n+1indicates that the RFIC 1902 has received message packet up to sequencenumber 11 and the expected seq_num of the next message packet to bereceived at the RFIC 1902 is 12.

FIG. 20 is a diagram illustrating an example of error and retry triggerby error on flow control message in accordance with various embodiments.In this example, an RFIC 2002 sends a FC message packet between messagepackets 6 and 7 to a BBIC 2004. During the transmission of the FCmessage packet, a bit error (e.g., CRC mismatch) occurs. In response tothe bit error on FC message, the BBIC 2004 discards the received messagepackets 7 and 8, and sends a NACK message to indicate the error on FCmessage packet. Upon reception of the NACK message at the RFIC 2002, theRFIC sends a FC message to the BBIC 2004. Subsequently, the RFIC 2002re-sends message packets 7 and 8 to the BBIC 2004.

FIG. 21 is a diagram illustrating an example of the sequence for writetransactions in accordance with various embodiments. WR_REQ initiatesthe sequence, ACK_RESP for the data channel indicates that WR_REQ wasreceived and data is posted to be committed to the destination. A singleflow control credit is maintained for all DL DATA transactions, and asingle flow control credit is used for all UL DATA transactions.

FIG. 22 is a diagram illustrating an example of the sequence for readtransactions in accordance with various embodiments. Read transactionsare treated as split transactions with type RD_REQ, RD_RESP pair andRD_DATA, RD_DATA_RESP pair. Each of the type pairs maintains separateflow controls with ACK scheme. Since messages and data are alwaysaccepted in sequence, this allows for each pair within the splittransaction to be tracked independently. In this example, the splittransaction is shown as 2 pairs separated in time, and each pair ishandled separately in error handling and retry.

RD_REQ initiates the sequence; RD_RESP indicates that RD_REQ has beenreceived. When RD_REQ is received the responder also activates RD_DATA.Once read data is retrieved from the source the read data is sent as adata packet (RD_DATA). When RD_DATA is received, RD_DATA_RESP is sentback. ACKs and flow control for RD_REQ, RD_RESP and RD_DATA,RD_DATA_RESP are handled separately.

Interrupt message transactions will have an INT message type and flowcontrol credit is similar to RD_REQ. The interrupt messages shall bearbitrated and stream across the message channels. The retry and errorhandling mechanism is same as RD_REQ. Power management messages are usedto support power state transitions of the serial interconnect. Errorsignaling messages are used to signal errors that occur on specifictransactions and errors that are not necessarily associated with aparticular transaction. These messages are initiated by the agent thatdetected the error.

FIG. 23 is a flowchart of a method of handling received packet inaccordance with various embodiments. The method may be performed by adevice (e.g., a BBIC or RFIC described herein). In one configuration, areceived packet is handled by this method when the received packet isdelivered to the receive transaction layer from the receive data linklayer, after the DLL has validated the integrity of the received packet.

At 2302, the device determines whether the packet follows format. If thepacket follows format, the device proceeds to 2304, otherwise proceedsto 2306.

At 2304, the device determines whether the type value of the packet isdefined. If the type value is defined, the device proceeds to 2308,otherwise proceeds to 2306.

At 2306, the device determines that the packet is bad, discards thepacket, and reports the bad packet. The method then ends.

At 2308, the device updates flow control tracking. At 2310, the devicedetermines whether the packet is a request. If the packet is a request,the device handles the request.

If the packet is not a request, the packet is completion and the devicehandles the completion.

FIG. 24 is a flowchart of a method of checking error for received packetin accordance with various embodiments. The method may be performed bythe DLL of a device (e.g., a BBIC or RFIC). At 2402, the devicedetermines whether the PCS indicated any received error for the packet.If at least one error is indicated, the device proceeds to 2406,otherwise proceeds to 2404. At 2406, the device discards the packet. Themethod then ends.

At 2404, the device calculates CRC using packet data received withoutCRC field. At 2408, the device determines whether the calculated CRC isequal to the received CRC in the packet. If the CRC matches, the deviceproceeds to 2410, otherwise proceeds to 2412.

At 2410, the device processes the packet. The method then ends. At 2412,the device discards the packet and reports error. The method then ends.

FIG. 25 is a flowchart of a method of handling received request inaccordance with various embodiments. The method may be performed by adevice (e.g., a BBIC or RFIC described herein). In one configuration, areceived request is handled by this method following the initialprocessing done with all transaction layer packets. At 2502, the devicedetermines whether the request type is supported. If the request type issupported, the device proceeds to 2506, otherwise proceeds to 2504.

At 2504, the device recognizes that the request is an unsupportedrequest. At 2508, the device determines whether the request requires acompletion. If the request requires a completion, the device proceeds to2510, otherwise the method ends. At 2510, the device sends completionand the method ends.

At 2506, the device determines whether the request type is MSG. If therequest type is MSG, the device proceeds to 2512, otherwise proceeds to2514.

At 2512, the device determines whether payload in MSG is defined. If thepayload in MSG is defined, the device proceeds to 2518, otherwiseproceeds to 2516.

At 2516, the device processes the MSG. The method then ends. At 2518,the device processes the MSG. The method then ends.

At 2514, the device determines whether the request violates protocol. Ifthe request violates protocol, the device proceeds to 2522, otherwiseproceeds to 2520.

At 2520, the device processes the request. At 2524, the devicedetermines whether the request requires a completion. If the requestrequires a completion, the device proceeds to 2526, otherwise the methodends. At 2526, the device sends completion and the method ends.

At 2520, the device determines whether the request requires acompletion. If the request requires a completion, the device proceeds to2528, otherwise the method ends. At 2528, the device sends completionand the method ends.

For read requests, data comes back as a data packet with a fix length of1024 bits whatever the number bits requested by the read request. TheLength field in the data packet header indicates the number of wordseffectively carried by the data packet: for data samples the payload isalways 32 words (1024 bits); and for CSR transactions the length willindicate the size in double-words of the burst to be generated.

In any split transaction protocol, there is a risk associated with thefailure of the requester to receive the expected completion. To allowrequesters to attempt recovery from this situation in a standard manner,a completion timeout mechanism is defined. This mechanism is intended tobe activated only when there is no reasonable expectation that thecompletion will be returned, and should never occur under normaloperating conditions.

The physical layer of the serial interconnect system implements thefollowing functions: 128b/130b encoding by providing sync symbolinsertion differentiating between PHY burst (physical layercommunication) or DLL burst; STMR synchronization from BBIC to the RFIC;Rx lane frame alignment and multi-lane deskew; equalization; trainingsequences for fast wakeup, hibernate wake-up, initial boot and recovery,involving equalization, CDR and alignment; physical layer tokeninsertion including idle link (IDL); maintenance of physical layerstatistics counters for tracking of PHY errors; low speed (LS) mode andhigh speed (HS) mode handling. The PHY handles the packetization andde-packetization of SERDES data from/into blocks of data that can befurther processed by the physical layer and upper layers; scramblingdata link layer communication (scrambling can be used to “whiten” EMIthe frequency content of the signals going over the serial interconnectand reduces radiated power at any one specific frequency and scramblingcan be done on a per lane basis); striping and de-striping of byte dataacross active lanes; and asynchronous clock crossing between the SERDESand the data link layer (controller) domain.

FIG. 26 illustrates an example timing diagram that can repeatperiodically in a one lane configuration every 130 UI (payload contentscan vary) in accordance with various embodiments. The 128b/130bencapsulation is handled within physical layer. There are two operatingmodes for the physical layer. Each operating mode is defined by its owntwo-bit sync header defining the specific operating mode of the link.Tokens for each operating mode are appended to each transfer to furtherclassify the data being sent across the link. The first operating modeis the packet burst, which is used for Data Link Layer communicationbetween a BBIC and an RFIC. The second type of operating mode is the PHYburst, used for Physical Layer communication. The distinction in betweenPacket and Lane is done by the two sync symbol bits: sync symbol 0x01indicates a Packet burst, and sync symbol 0x10 indicates a PHY burst.

Packet Burst are used for Data Link Layer communication. The packetbursts can contain data and configuration data in the form of a datapacket, or interrupts, DLL communication, ACKs/NACKs, pings, and datarequests in the form of messages. Packet bursts are defined by a two-bitsync header (0x01). An 8-bit token differentiates packet types. Thetoken is located in the first byte of each transfer after the syncsymbol. In packet bursts, the sync symbol is not scrambled, while thetoken and payload are always scrambled.

Packet bursts have two subtypes: message packet, including interrupts,ACKs/NACKs, read request, ping, and DLL communication; and data packets,memory mapped transfers, configuration accesses and IQ sample data.

The Packet Burst format follows these rules: the token, which is 8 bits,is scrambled and is triple-bit-flip protected, the payload is scrambledand CRC protected, and the EPB token must be sent as indication toswitch to PHY burst and is required to be the last byte transmittedbefore switching to PHY burst operating mode, no idles can come betweenthis token and a PHY burst header. An example list of packet bursttokens in accordance with various embodiments is described in Table 7below:

TABLE 7 List of Packet Burst Tokens Token Value Comment IDL (Idle) 00hIdle tokens are used for periods in packet burst mode when noinformation is being transmitted across the link. The Idle pattern isalso used for BER profiling as the error for idle tokens is detected perindividual lane DPT (Data Packet FFh Data Packet transfer tokenTransfer) is used for data transfers of 1080 bits in length. 1024 bitsof payload, and 64 bits of header/CRC MPT (Message 0Fh The Message Tokenis Packet Transfer) used for ACK/NACKs, DLL communication, readrequests, pings and interrupts. Messages are 56 bits in length EPB (Endof F0h Token to indicate the Packet Burst) switch from Packet Burst toPHY burst operating mode

FIG. 27 illustrates examples of byte striping enabled 2700 across threelanes and of byte striping disabled 2750 in accordance with variousembodiments. In byte striping enabled 2700, each byte in the transfer issent in successive lanes. For example, the MPT token is sent in lane 0,the first byte following the MPT token is sent in lane 1, the secondbyte following the MPT token is sent in lane 2, the third byte followingthe MPT token is sent in lane 0, and so on.

A scrambler can significantly lower the probability of long run-lengthsof consecutive zeros or ones. The scrambler also spreads the powerspectrum and thus can avoid spurs at discreet frequencies.

The serial interconnect system shall support a scrambler with thefollowing generator polynomial:

G(X)=X ²³ +X ²¹ +X ¹⁶ +X ⁸ +X ⁵ +X ²+1

The repetition period of this scrambler is 2²⁴−1 UIs=16,777,215. Onlydata bytes shall be scrambled, synchronization symbols and tokens remainunscrambled. The number of bits in a frame being 128, the repetitionperiod is therefore 131,072 frames.

The scrambler is reset by using a special payload in the SPB token atthe end of a PHY Burst, the scrambler will update on every byteindependent of the data on each byte, except for when using the BSV PHYburst. In that manner, both transmitter and receiver should never getout of sync. Bit errors on the link may occur but assuming the number of130-bit patterns match on transmitter and receiver the LFSRs shouldalways match. Some example configurations include: the scrambleroperates independently per lane, and one scrambler per lane; thescrambler is used in packet layer data and PHY transfer BSV; 2-bit syncsymbols, token and PHY Bursts data are not scrambled; each byte of datais scrambled by a unique 24-bit LFSR value; the LFSR value is frozen andbroadcast during the BSV PHY burst; tokens and sync symbols are neverscrambled in PHY burst mode, and tokens are scrambled in packet burstmode; special payload on the SPB token resets the scrambler, and thereset is used when errors cause the transmitter and receiver to be outof sync.

FIG. 28 illustrates a data packet format 2800 and a message packetformat 2850. Byte 1111_1111b indicates Data Packet Transfer (DPT) token.This token is used to frame a data packet carrying data samples,configuration data, DLL data or other memory-mapped data between theRFIC and the BBIC. DPT is sized 1088 bits (8-bit token+1080 data packetpayload). Details for the data packet payload structure are describedabove with reference to FIG. 9.

Byte 0000_1111b indicates Message Packet Transfer (MPT) token. Thistoken is used to frame a message packet as part of a packet burst.Message packet transfers are used to transmit interrupts, ACKs/NACKs,read request, ping, and DLL communication between the RFIC and the BBIC.MPT is sized 64 bits (8-bit token+56 bit message packet payload).Details of the message packet payload structure are described above withreference to FIG. 9.

Byte 0000_0000b indicates Idle (IDL) link token. The idle token is usedduring packet bursts to fill in the gaps not occupied by messagestransfers, data transfers or End of Packet Burst token during a packetburst transmission. This packet is scrambled. Ping Pattern used todetect the state of the link and run BER analysis per lane The IDLEpattern is also used to send a known payload scrambled sequence acrossall lanes on a link, because each lane is required to have separatescrambler logic with a different LFSR pattern, this setup allows forindependent error profiling on each individual lane.

EPB Token, denoted by 1111_0000b is used to delineate the switch fromData link layer communication to Physical Layer communication. Thistoken has to be the very last data byte prior to switching to PhysicalLayer communication (PHY burst operating mode).

PHY Bursts are used for Physical Layer communication. The PHY bursts cancontain Equalization, CDR and alignment information, indicate the startof a packet burst, signal the start or end of a transmission, send theuniversal timer value across the link and provide ways for the tracetools to track the LFSR pattern in the scrambler.

PHY bursts are defined by a two-bit sync header (0x10). An 8-bit tokendifferentiates PHY layer communication types. The token is located inthe first byte of each transfer after the sync symbol. In PHY bursts,neither the token nor the payload is scrambled.

PHY bursts have multiple subtypes for PHY to PHY communication:STS—System Timer Synchronization; SPB—Start of packet burst;BSV—Broadcast Scrambler Value; EOT—End of Transmission; SOT—Start ofTransmission; SYNC—Start of CDR in high speed mode; EQ—EqualizationPattern

The PHY Burst format follows these rules: the token, which is 8 bits, isnot scrambled; the payload not scrambled for any PHY Burst; all burstsconsist of 1 frame of data (130 bits) per active lane, except for theBSV which can be of variable length; all Lanes of a multi-lane link musttransmit frames with the same sync symbol and token simultaneously; thepayload will be either a repeated pattern per byte or triple redundantdepending on the transfer type; the SPB token must be sent as indicationto switch from PHY burst to packet bursts and the SPB token is requiredto be the last byte transmitted before switching to packet burstoperating mode; the LFSR is not advanced for the bytes of the BSVordered set, and they are advanced for all other bytes.

An example PHY burst token list in accordance with various embodimentsis shown in Table 8 below:

TABLE 8 PHY Burst Token List Token Value Comment STS (System Timer 2DhSTMR Synchronization Synchronization) Lane packet. Sends STRM value fromBBIC to RFIC SPB (Start of Packet E1h, Last frame before burst) (55h)x15switching operating modes from PHY burst to Packet burst BSV (BroadcastAAh Token to provide a known Scrambler Value) pattern which broadcaststhe LFSR settings to aid trace tools EOT (End of (66h)x16 Last framebefore putting Transmission) the lane into Electrical Idle SOT (Start of(00_FFh)x8 Frame used to End Transmission) electrical Idle and start thelink bring up into either PHY burst or packet burst operating modes SYNC(Lane 1Eh Training sequence sychronization) providing CDR EQ(Equalization 55h Equalization pattern to be Pattern) sent out to helpthe receivers equalize preventing inter-symbol interference

2Dh defines the STMR Synchronization token (STS). The STMSsynchronization transfer is used to synchronize the Universal Timervalue between the BBIC and the RFIC. The value delivered is tripleredundant and the value is sent along with the up-sampled phase PO ofthe STMR counter into the RFIC to allow for proper synchronizationbetween components.

E_1h indicates the Start of Packet burst (SPB). This token is used totransition from PHY burst to packet burst mode and Data Link Layercommunication. The start of packet burst is the last frame sent on alane before switching to the packet burst operating mode.

The broadcast scrambler value PHY burst sends the LFSR value for helpingtrace tools achieve block alignment. The value is sent in a tripleredundant manner. The LFSR value does not advance on each byte duringthe BSV transfer as the LFSR value would during any other transfer. BSVwill provide the LFSR scrambler value on a per lane basis.

Token 66h indicates the End of Transmission during PHY burst operatingmode. This token is sent out before the transmitter goes into ElectricalIdle. The Receiver of the EOT token should ignore all data after the EOTToken has been received until the EQ, SYNC or SOT tokens are received.

The start of transmission is delimited by a frame with a low frequency0->1->0->1 pattern. The pattern is used for lane and block alignmentprior to starting any other non-initialization traffic on the link. Thispattern is also used to restart the scrambler logic prior to startingpacket burst mode operation

Sync pattern using a frame full of bytes using the AAh pattern is usedfor clock and data recovery by the receiver. The frame will be sent outas many times as needed by the link. During first initialization of thelink in low speed mode, the number of CDR frames required to be senteach time the link is initialized must be configured.

The Equalization pattern is used to reduce inter-symbol interference andallow the reliable recovery of the transmitted data in the link. Theequalization frame consists of A5h pattern which uses the scrambler'sLFSR pattern to aid the analog circuitry complete the equalizationprocess in an optimal manner. The number of EQ frames to be sent duringthe equalization procedure must be programmed via messaging.

The mapping rules from frames to physical lanes are complex, below areillustrated two examples of bursts mapping into the physical lanes ofthe link. In Table 10, the mapping of packet bursts can be observed. InTables 9 and 10 below, example PHY bursts in accordance with variousembodiments are depicted:

TABLE 9 Packet Burst Mapping to Physical lanes Lane 0 Lane 1 Lane 2PACKET - Sync Character: 01 01 01 bit BURST 0x01 (Packet Burst) FrameEach lane Sends a 0000 1111 MSG - B0 MSG - B1 Frame, data is byte (MPT)stripped across all MSG - B2 MSG - B3 MSG - B4 active lanes MSG - B5MSG - B6 1111 1111 Token + MSG + (DPT) Token + Data Data - B0 Data - B1Data - B2 Data - B3 Data - B4 Data - B5 Data - B6 Data - B7 Data - B8Data - B9 Data - B10 Data - B11 Data - B12 Data - B13 Data - B14 Data -B15 Data - B16 Data - B17 Data - B18 Data - B19 Data - B20 Data - B21Data - B22 Data - B23 Data - B24 Data - B25 Data - B26 Data - B27 Data -B28 Data - B29 Data - B30 Data - B31 Data - B32 Data - B33 Data - B34Data - B35 Data - B36 Data - B37 Data - B38 Sync Character 01 01 01(Packet Burst) Frame 3, 4, 5 Data - B39 to Data - B87 Sync Character 0101 01 (Packet Burst) Frame 6, 7, 8 Data - B88 to Data - B136 SyncCharacter 01 01 01 (Packet Burst) Message only Packet 0000 1111 S0 - B1S0 - B2 (MPT) S0 - B3 S0 - B4 S0 - B5 IDLE to align S0 - B6 S0 - B7 00000000 (IDL) 13 Bytes of IDL 0000 0000 0000 0000 0000 0000 tokens per laneto (IDL) (IDL) (IDL) get to the frame boundary in each lane SyncCharacter 01 01 01 (Packet Burst) Data Packet only 1111 1111 Data-B0Data-B1 (136 Bytes) (DPT) Data-B2 Data-B3 Data-B4 Data-B5 to Data-B46 0101 01 Data-B47 to Data-B95 01 01 01 Data-B96 to Data-B135 Data-B136 00000000 0000 0000 (IDL) (IDL) 0000 0000 0000 0000 0000 0000 (IDL) (IDL)(IDL) Last byte is used to 0000 0000 0000 0000 1111 0000 insert a tokento (IDL) (IDL) (EPB) switch to PHY burst Sync Character 10 10 10 (PHYburst)

TABLE 10 PHY Burst mapping to Physical Level Lane 0 Lane 1 Lane 2 LaneSync Character 10 10 10 130 Burst (Lane Burst) EOT EOT EOT bit In Laneburst, EOT EOT EOT Frame communication EOT EOT EOT per happens per lane.EOT EOT EOT lane Here we have one EOT EOT EOT frame of electrical EOTEOT EOT idle start per lane EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOTEOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOT EOTEOT Sync Character 10 10 10 130 (Lane Burst) bit SOT SOT SOT Frame . . .. . . . . . per SOT SOT SOT lane 10 10 10

FIG. 29 illustrates an example data link layer and physical layertransmission at a single physical lane 2902 in accordance with variousembodiments. In this example, a PHY burst 2910 is followed by a packetburst that includes packets 2904 and 2906. The PHY burst 2910 ends witha SPB token 2914, which indicates the last frame before switchingoperation mode from PHY burst to packet burst. There are several IDLtokens 2916 transmitted between the packets 2904 and 2906. The packet2906 is followed by an EPB token 2918, which indicates the switch frompacket burst to PHY burst operating mode. The EPB token 2918 is followedby a PHY burst 2912, which is followed by another packet burst thatincludes packet 2908. The packet 2908 is followed by an EPB token 2922,which is followed by an EOT token 2920, which indicates the last framebefore putting the lane 2902 into electrical idle.

FIG. 30 illustrates an example data link layer and physical layertransmission at three physical lanes 1-3 in accordance with variousembodiments. In this example, each of the physical lanes 1-3 starts witha PHY burst 3010. For each frame in the PHY burst 3010, thesynchronization symbol is ‘10’. The PHY burst 3010 is followed by apacket burst 3012. For each frame in the packet burst 3012, thesynchronization symbol is ‘01’. The packet burst 3012 includes a messagepacket 3001 and three data packets 3002-3004. The packets byte strippedover the physical lanes 1-3. Each packet is started with a token. Forexample, the message packet 3001 is started with a MPT token 3020 andthe data packet 3003 is started with a DPT token 3022. The packet burst3012 is followed by an EOT token 3026 on each of the lanes 1-3.

The link Equalization is done during first bring up of the link afterpower up. The purpose of equalization is to reduce inter-symbolinterference to ensure the reliable recovery of high speed transmitdata. Equalization must be done every time the link is powered down andpowered back up before operating in high-speed mode, and it is notnecessary to be performed at any other time. In one configuration, linkequalization may be done at any time while in PHY burst mode.Equalization time is variable and will change from chip to chip and partto part depending on technology and process skew. The amount of time thelink spends in the equalization procedure is configurable via low speedmode programming. Equalization may be required to occur when the firsttime the serial interconnect to wake up from high speed deep sleep statebefore moving to any other high speed state.

The Clock Data Recovery (CDR) sequence adjusts the receiver setup ofeach lane to improve the signal quality and meet the required signalintegrity by aligning the clock with the center of the data eye. CDRmust be executed during the first HS wake up of the serial interconnect.Even if CDR is not required to be repeated for reliable operation ateach transition of any of the sleep to active modes, DLL will have theoption of repeating the procedure at any time. CDR can be required afterthe following conditions: first time the link moves from LS to HSoperation; each transition out of HS Sleep to HS burst; each transitionout of HS Deep Sleep.

Lane alignment is used to reliably construct data in the receiver afterthe data has been processed by the de-serializer to detect the frameboundary. Block alignment is used to reliably construct logical data bydetecting the appropriate skew between each of the data lanes in a link.

FIG. 31 illustrates an example state machine that can be used to trackthe status of a high-speed serial link in accordance with variousembodiments. At a device power up 3100, the link enters a power us state3101. The link can transition to a slave detect state 3103. From slavedetect state 3103, the link can transition to a configuration state3105. From configuration state 3105, the link can transition to anactive state 3107. Additional states include a light sleep state 3109, adeep sleep state 1311, and a recovery state 3113. The movement betweenstates is determined by a variety of external factors includingsequences, external inputs and errors.

Two sideband signals can be used to control the operation states of theserial interconnect. These signals can be low speed, mainly static,signals that indicate in which state the serial interconnect is inand/or in which state the serial interconnect will move to. In someembodiments, the sideband signals can be link_en and link_req asdescribed above with reference to FIG. 2. In this example, link_en canbe sent from master (e.g., BBIC) to slave (e.g., RFIC), and can have twouses, the first at cold boot, and the second during standard operation.At cold boot, a sequencer at the slave side can use a ROM Code to bootfollowing the policy defined, link_en, as input to the slave, isexpected to be ‘0b. In the case link_en is set to ‘1b at power-on reset(POR), then the normal boot sequence will not execute, and the slavewill enter a “test/debug” modes, and based on general-purposeinput/output (GPIO) setting at POR, the RF front end (RFFE) or otherdebug features will be activated. During operation, the RFIC can be theslave of the BBIC, and the SERDES PHY clock can be provided by BBIC. Theonly way for slave to know if the SERDES clock is available, ready foroperation, meaning the SERDES clock can be used by the slave SERDES PHYis to detect a 1b on link_en. Therefore, following the power policy, amaster sequencer will assert link_en accordingly to the state of theSERDES PHY clock.

With regard to the link_req signal, this signal can be sent from theslave (e.g., RFIC) to the master (e.g., BBIC). When the serialinterconnect has been turned down, i.e., put in sleep mode to savepower, but slave is still active, such that RxFE, TxFE arecreating/consuming data and interrupts/events are being generated, theslave may need to send information to master before the standard wake uppolicy controlled by master put back the serial interconnect active. Tohave traffic re-established, a link_req will be controlled by the slavesequencer and will trigger the master sequencer to wake-up the serialinterconnect, meaning re-starting HS mode traffic following the definedpolicy.

An example list of link power management states in accordance withvarious embodiments is shown in Table 11 below:

TABLE 11 Example link power management states PHY Block Q0 Q1 Q2 Q3 Q4Tx Normal HS mode ON: On: On: Power down All sub-blocks On Internaldividers Electrical idle Electrical idle All termination Clock bufferDriver LDO Off: in high-Z Electrical idle Off: All others Driver LDOOutput driver Off: in high-Z Output driver Serializer in high-Z Clockbuffer Serializer Rx ON: On: Power down na Internal dividers Signaldetect All termination Clock buffer Off: in high-Z Signal detect Clockbuffer Off: Input receiver Input receiver Deserializer DeserializerMaster On: On: Power down na Clock DLL Electrical idle All terminationElectrical idle Bias in high-Z Bias Off: Off: DLL Output driver Outputdriver Slave On: Power down na na Clock Clock signal All terminationdetection in high-Z Off: Input Receiver PLL active disable na na na

Example power states based on the power state definitions in Table 11 inaccordance with various embodiments are shown in Table 12 below:

TABLE 12 Example power states LINK SYSTEM STATE SETUP RFIC_TX0 RFIC_TX1RFIC_TX2 RFIC_CK0 RFIC_RX0 RFIC_POWER (mW) RFIC_EXIT_LATENCY BBIC_RX0 1Q0 Q0 Q0 Q0 Q0 16.8 NA Q0 2 Q1 Q1 Q1 Q0 Q1 7.9 ~1 ns Q1 3 Q2 Q2 Q2 Q1 Q21.2 ~40 ns + Q1 Controller Needs to re-align 4 Q2 Q2 Q2 Q1 Q2 1.2 ~40ns + Q2 Controller Needs to re-align 5 Q3 Q3 Q3 Q1 Q3 0.4 ~100 ns + Q3Controller Needs to re-align 6 Q3 Q3 Q3 Q1 Q3 0.37 ~100 ns + Q3Controller Needs to re-align 7 Q4 Q4 Q4 Q2 Q3 0.13 Needs Q3 Reset Pin toWake up. +110 ns LINK SYSTEM STATE SETUP BBIC_RX1 BBIC_RX2 BBIC_CK0BBIC_PLL BBIC_TX0 BBIC_POWER (mA) BBIC_EXIT_LATENCY 1 Q0 Q0 Q0 Q0 Q017.5 NA 2 Q1 Q1 Q0 Q0 Q1 10.0 ~1 ns 3 Q1 Q1 Q1 Q0 Q1 7.9 ~1 ns 4 Q2 Q2Q1 Q0 Q2 4.1 ~40 ns + Controller Needs to re-align 5 Q3 Q3 Q2 Q0 Q3 1.8~100 ns + Controller Needs to re-align 6 Q3 Q3 Q3 Q1 Q4 0.13 ~2 us +Controller Needs to re-align 7 Q3 Q3 Q3 Q1 Q4 0.13 ~2 us + ControllerNeeds to re-align

QL0 can be a high speed operational link. Data and messages can bereceived and transmitted. Speed, configuration (number of lanes), andsupported power saving capabilities can be previously negotiated. Themaster can send a ping to slave on entry to QL0 state from QL1 (i.e.there was a change in link speed). QL0 may have one or more QL0xsub-states allowing some low latency power saving if link isunidirectional for some period of time. QL0ls can be a high speed lightsleep. One or both sub-links can have transmitter in electrical idle,while other party's receiver is on and ready to receive data. QL0s canbe a high speed sleep. One or both sub-links can have transmitter inelectrical idle, while other party's receiver is in sig_det mode. QL0pcan be a high speed link power down/hibernate/deep sleep. Power can bemore aggressively conserved in QL0p at the expense of increased resumelatency. Zero or more QL0p states may be defined but if one or more QL0pstates are supported, transitions between these states must pass throughQL0.

QL0l can be a high speed loopback test modes. Transition to this statecan occur from QL0 state. Transition out of this state can be to QL0p orQL0 and is left up to the implementation.

QL1 can be a base speed operational link. A mandatory base capabilitycommunication link can be supported by all current and future devices.It is envisioned that this is a single lane full duplex (dual simplex)link operating at the lowest supported speed of all devices. The masterwould send a ping to slave on entry to QL1 state from QL0 (i.e. therewas a change in link speed) or from QL2 (device power up, first timelink is up since reboot). QL1 may have one or more QL1x sub-statesallowing some low latency power saving if link is unidirectional forsome period of time. QL1ls can be a low speed light sleep. One or bothsub-links can have transmitter in electrical idle, while other party'sreceiver is on and ready to receive data. QL1s can be a low speed sleep.One or both sub-links can have transmitter in electrical idle, whileother party's receiver is in sig_det mode. QL1p can be a base link powerdown/hibernate/deep sleep. Zero or more QL1p states may be defined butif one or more QL1p states are supported, transitions between thesestates must pass through QL1.

QL1l can be a base speed loopback test modes. Transition to this statecan occur from QL1 state. Transition out of this state can be to QL1p orQL1 and is left up to the implementation.

QL2 can be a device power up, no link available. This is the state ofthe device immediately after boot, for example.

FIG. 32 is an example state diagram showing example power states andpower state transitions in accordance with various embodiments. At 3201,the device powers up into state QL2 (3201). From QL2 (3201), the devicecan transition to QL1s (3203) LS Sleep by the following method. MasterClock on LS, Rx active, Tx electrical idle, link_en asserted. Slavedetects link_en, turns on Clock receiver, Rx Signal Detect/Tx active.Slave sends alignment pattern once 5x130 bits and goes to Tx electricalidle, Rx sig_det, Rx clock active (LS Sleep). When master detectsalignment, the master moves to LS Sleep.

From QL1 (3205) LS Burst the device can transition to QL1ls (3207) LSLight Sleep by the following method. Initiator detects nothing to sendand switches Tx to electrical idle. Follower leaves receiver in activestate.

From QL1ls (3207) LS Light Sleep the device can transition to QL1 (3205)HS Burst by the following method. Initiator detects something to sendand switches Tx to active state. Follower leaves receiver in activestate.

From QL1s (3203) LS Sleep, which is a timed option the device cantransition to QL1 (3205) LS Burst by the following method. Initiatorsends N EoEI (end of electrical idle) sequences. Follower detectssig_det, switches Rx to active mode.

From QL1s (3203) LS Sleep, which is a follower response option thedevice can transition to QL1 (3205) LS Burst by the following method.Step 1: I: Check to see if Rx Sub-link is active. If RxsubLinkActive==0;FS2 I: RxsubLinkActive==0, Follower Sleeping; FS3 I: Rx Q0, Tx Drive 1;FS4 F: Sig Detect; FS5 F: Rx Q0, Tx Drivel; FS6 I: Sig_det; FS7 I: TxAlignment; FS8 F: Alignment Done; FS9 F: Tx Alignment; FS10 I: AlignmentDone; FS11 BBIC: Send Ping; FS12 RFIC: ACK/NACK; FS13 F: Sleep ifnothing to send; else; FA2 I: RxSubLinkActive==1, Follower Awake; FA3 I:Rx Q0, Tx Drive 1; FA4 F: Sig Detect; FA5 F: Tx Send Message; FA6 I:Wait message—if Rx sig_det drops, move to other track, FS 6; FA7 I: TxAlignment; FA8 F: Alignment done; FA9 F: Send Ready MSG Pass/Fail; FA10I/F: If NACK, goto FA7.

From QL1 (3205) LS Burst the device can transition to QL1s (3203) LSSleep by the following method. Burst Msg SoEI (start of electricalidle)—sender then puts Tx to electrical idle, recipient of msg puts Rxto sig_det mode.

From QL1p (3209) LS Deep Sleep/Hibernate the device can transition toQL1s (3203) LS Sleep by the following method. Process started withlink_en or link_req. If Hibernating, master configs PLL. Master startsTx of HS clock, Rx active, Tx electrical idle, link_en asserted. Slavedetects link_en, turns on Clock receiver in HS mode, Clock calibration,Rx Signal Detect, Tx active. Slave sends alignment pattern once—5x130bits and goes to Tx electrical idle, Rx sig_det, Rx clock active (LSSleep). When master detects alignment, the master moves to LS Sleep.

From QL1 (3205) LS Burst the device can transition to QL1p (3209) LSDeep Sleep/Hibernate by the following method. Master sends LS HIBERNATEmessage to slave, slave acks. Master turns off Rx to off. Master puts Txin EI. Slave drops Tx, Rx to off, and disables clock input. Masterde-asserts link_en. Master turns off clock block and Tx block.

From QL1 (3205) LS Burst the device can transition to QL0p (3211) HSDeep Sleep/Hibernate by the following method. Master sends HS HIBERNATEmessage to slave, slave acks. Master turns off Rx to off. Master puts Txin EI. Slave drops Tx, Rx to off, and disables clock input. Masterde-asserts link_en. Master turns off clock block and Tx block.

From QL1p (3209) LS Hibernate the device can transition to QL3 (notshown, equivalent to QL2, power off) by the following method. Masterreceived power down cmd from Q6, master informed slave to enterhibernate with power down expectations (no wake-up), master informs Q6when both are in hibernate and enters Q3 terminal state.

QL0p (3211) HS Hibernate the device can transition to QL3 (power off) bythe following method. Master received power down cmd from Q6, masterinformed slave to enter hibernate with power down expectations (nowake-up), master informs Q6 when both are in hibernate and enters Q3terminal state.

From QL0 (3213) HS Burst the device can transition to QL1p (3209) LSDeep Sleep/Hibernate by the following method. Master sends LS HIBERNATEmessage to slave, slave acks. Master turns off Rx to off. Master puts Txin EI. Slave drops Tx, Rx to off, and disables clock input. Masterde-asserts link_en. Master turns off clock block and Tx block.

From QL0 (3213) HS Burst the device can transition to QL0p (3211) HSDeep Sleep/Hibernate by the following method. Master sends HS HIBERNATEmessage to slave, slave acks. Master turns off Rx to off. Master puts Txin EI. Slave drops Tx, Rx to off, and disables clock input. Masterde-asserts link_en. Master turns off clock block and Tx block.

From QL0p (3211) HS Deep Sleep/Hibernate the device can transition toQL0s (3215) HS Sleep by the following method. Process started withlink_en or link_req. If Hibernating, master configs PLL. Master startsTx of HS clock, Rx active/CDR enable, Tx electrical idle, link_enasserted. Slave detects link_en, turns on Clock receiver in HS mode,Clock calibration, Rx Signal Detect/CDR, Tx active. Slave sends CDRpattern, alignment pattern once—5x130 bits and goes to Tx electricalidle, Rx sig_det, Rx clock active (HS Sleep). When master detectsalignment, the master moves to HS Sleep.

From QL0p (3211) HS Deep Sleep/Hibernate, with equalization (first timesince cold boot), the device can transition to QL0s (3215) HS Sleep bythe following method. Process started with link_en. Must be carriedthrough on first transition from cold boot, so BBIC is drivingtransition to get EQ done. Similar to regular hibernation to sleeptransition except both sub-links must be brought up with eq, and a pingsent from BBIC. If Hibernating, master configs PLL. Master starts Tx ofHS clock, Rx active/CDR enable, Tx electrical idle, link_en asserted.Slave detects link_en, turns on Clock receiver in HS mode, Clockcalibration, Rx Signal Detect/CDR, Tx active. Both send eq pattern forspecified time, CDR pattern for specified time, and alignment patternonce. BBIC sends ping RFIC sends ACK. Both then set Tx electrical idle,Rx sig_det, Rx clock active (HS Sleep).

From QL0 (3213) HS Burst the device can transition to QL0ls (3217) HSLight Sleep by the following method. Initiator detects nothing to sendand switches Tx to electrical idle. Follower leaves receiver in activestate.

From QL0ls (3217) HS Light Sleep the device can transition to QL0 (3213)HS Burst by the following method. Initiator detects something to sendand switches Tx to active state. Follower leaves receiver in activestate.

From QL0s (3215) HS Sleep, which is a timed option the device cantransition to QL0 (3213) HS Burst by the following method. Initiatorsends N EoEI (end of electrical idle) sequences. Follower detectssig_det, switches Rx to active mode, with Rx CDR enabled. Followerdetects alignment and disables Rx CDR.

From QL0s (3215) HS Sleep, which is a follower response option thedevice can transition to QL0 (3213) HS Burst by the following method.Step 1: I: Check to see if Rx Sub-link is active. If RxsubLinkActive==0;FS2 I: RxsubLinkActive==0, Follower Sleeping; FS3 I: (Rx is already insig_det), Tx Drive 1; FS4 F: Sig Detect rises; FS5 F: Rx Q0/CDR enable,Tx drive CDR pattern; FS6 I: Sig_det rises, RxQ0/CDR enable, Tx driveCDR pattern; FS7 I: waits CDR timer value, then sends Tx Alignment; FS8F: Alignment Done; FS9 F: waits CDR timer value, then sends TxAlignment; FS10 I: Alignment Done; FS11 BBIC: Send Ping; FS12 RFIC:ACK/NACK; FS13 F: Sleep if nothing to send; else; FA2 I:RxSubLinkActive==1, Follower Awake; FA3 I: Tx Drive 1; FA4 F: Sig Detectfalling; FA5 F: Tx Send Message; FA6 I: Wait message—if Rx sig_detdrops, move to other track, FS 6; FA7 I: Tx CDR/Eq pattern, thenAlignment; FA8 F: Alignment done; FA9 F: Send Ready MSG Pass/Fail; FA10I/F: If NACK, goto FA7.

From QL0 (3213) HS Burst the device can transition to QL0s (3215) HSSleep by the following method. Burst Msg SoEI (start of electricalidle)—sender then puts Tx to electrical idle, recipient of msg puts Rxto sig_det mode.

There are various methods of implementing power state transitions inaccordance with various embodiments. For example, a method to power upstate QL2 can be implemented by top level powers up link devices. Amethod to do minimal boot and wait for other party if needed can beimplemented by sideband signal link_en is used to initiate bootsequence. A method to setup a minimal base communication link, QL1 canbe implemented by ROM code on slave, PDMEM loaded by top level onmaster. Methods to retrieve slave device capabilities, connectionconfiguration, rate capabilities, supported power states configurationdetails, supported test and loopback states, error detection andhandling procedures, boot parameters can be implemented by messagesignaling and memory reads over low speed link for device capabilities,memory write and jump message from master to slave, etc., as necessary.A Master SEQ can determine QL0 parameters based the Master SEQ's owncapabilities and slaves capabilities. A Master SEQ can determine errordetection and handling parameters based the Master SEQ's owncapabilities and slaves capabilities. A method to signal chosen rate andconfiguration for QL0 to slave can be implemented by Master message toslave. A method to initiate change of speed from QL1 to QL0 can beimplemented by master message to slave. A method to signal state changesfrom between sub-link active to sub-link sleep can be implemented byinitiator of traffic moves Tx from Q1 to Q0, and the recipient candetect a change in state using phy Rx signal detect. A method to signalstate changes from QL0 to QL0p. or QL1 to QLp can be implemented. Innormal operation, the master can indicate mandatory transitions usingmessages. In error recovery, the master can indicate mandatorytransitions using link_en. A method to signal change to loopback teststate can be implemented by the master indicating transition usingmessage to slave. A method to signal change from loopback test state todeep sleep can be implemented, depending on loopback mode, by the masterindicating transition using a message to the slave (assuming slave canmonitor loop-back data for messages), or by a timer ending state.

FIG. 33 is a diagram illustrating an example of a master inter-devicelink PHY block 3318 and an example of a slave inter-device link PHYblock 3316 in accordance with the systems and methods described herein.The slave inter-device link PHY block 3316 includes a PCS and controller3302 that may be used to control the functionality within the slaveinter-device link PHY block 3316. The PCS and controller 3302 mayreceive uplink data from a serial-to-parallel converter 3304 that iscoupled to a receive block 3306. The receive block 3306 may receiveserial data over the uplink from the master inter-device link PHY block3318. The serial data received by the receive block 3306 may beconverted to parallel data using the serial-to-parallel converter 3304.The PCS and controller 3302 may then read the parallel data from theserial-to-parallel converter 3304. The serial-to-parallel converter 3304may be driven by a clock and data recovery (CDR) block 3310. A singleuplink channel is used. It will be understood that in other examplesmore uplink channels may be used. Further, it will be understood thatsystems that are intended for receive only functionality may not includean uplink.

The PCS and controller 3302 may send downlink data to the masterinter-device link PHY block 3318 using a series of parallel-to-serialconverters 3316 and transmit blocks 3308. For example the PCS andcontroller may write parallel data to one or more of theparallel-to-serial converters 3316. The parallel-to-serial converters3316 may convert any parallel data received to serial data fortransmission by the transmit block 3308. In the illustrated example ofFIG. 33 there are three downlink channels that the PCS and controllermay choose between when sending data to the master inter-device link PHYblock 3318. It will be understood that more downlink channels or fewerdownlink channels may be used in a particular implementation. Forexample, systems that are intended to transmit only may not include anydownlink. Generally, however systems will have a mix of uplink anddownlink channels.

The slave inter-device link PHY block 3316 includes a clock receiver3314 that is coupled to the master inter-device link PHY block 3318 andmay receive a clock from the inter-device link master. Using a commonclock between the master inter-device link PHY block 3318 and the slaveinter-device link PHY block 3316 may allow the slave inter-device linkPHY block 3316 and the master inter-device link PHY block 3318 to besynchronized with each other or nearly synchronized with each otherdepending on any delay that may be present in the clock path. The clockreceiver 3314 inputs the received clock signal to the slave clock block3312 which may be used to distribute the clock to the parallel-to-serialconverters 3316 and the CDR block 3310.

The master inter-device link PHY block 3318 includes a PCS andcontroller 3322 that may control the inter-device link master 3318. ThePCS and controller 3322 may send data through the uplink to the slaveinter-device link PHY block 3316 by writing parallel data to theparallel-to-serial converter 3324. The parallel-to-serial converter 3324may convert the parallel data to serial data that may be input into thetransmit block 3326. The transmit block 3326 in the master inter-devicelink PHY block 3318 may then transmit the data serially along the uplinkto the slave inter-device link PHY block 3316 where the data is receivedby the receive block 3306. Downlink data may be received by the masterinter-device link PHY block 3318 at receive block 3338. The receiveblocks 3338 are each coupled to a serial-to-parallel converter 3324which are each controlled by a CDR 3340. The serial-to-parallelconverters 3324 may convert any serial data received from the receiveblock 3338 to parallel and the parallel data may be read by the PCS andcontroller 3322.

The master inter-device link PHY block 3318 may include a master clockblock 3332 which may be used to generate a clock signal. The clocksignal generated by the master clock block 3332 may be distributed tothe CDRs 3340 and the parallel-to-serial converter 3324. Additionally,the master clock block 3332 may distribute a clock to the clock driverto 3334 which may then transmit a clock signal to the slave inter-devicelink PHY block 3316. The master clock block 3332 may be coupled to a PLL3336 which may be used as part of the clock generating process.

As described above, the master inter-device link PHY block 3318 includesa PCS and controller 3322. Additionally as also described above theslave inter-device link PHY block 3316 also includes a PCS andcontroller 3302. Each of the PCS and controller 3322, 3302 may include aprocessor such as a microprocessor, a microcontroller, a digital signalprocessor (DSP), or other programmable controller. By using a controllerthat is programmable such as, for example, a microcontroller, the linkbetween the master and slave may be reconfigurable. The controllers3302, 3322 may include a programmable processor configured to implementa programmable state machine. The programmable state machine may beconfigured to control at least one of initiation of the physical layerlink, bit alignment of a signal received by a receiver, bit alignment ofa signal transmitted by a transmitter, training, power management,testing, loop-back modes, debugging modes, error handling,phase-locked-loop initialization, or reset handling and wherein thefunctionality of the at least one of initiation of the physical layerlink, bit alignment of a signal received by the receiver, bit alignmentof a signal transmitted by the transmitter, training, power management,testing, loop-back modes, debugging modes, error handling,phase-locked-loop initialization, or reset handling is programmable byreprogramming the programmable processor such that at least one of aboot up sequence, power management protocol, or testing protocol isreconfigurable.

FIG. 34 is a conceptual block diagram illustrating a pair of examplecontrollers in accordance with the systems and methods described herein.A processing system 3400 includes the PCS and controller 3302 of slaveinter-device link PHY block 3316 and the PCS and controller 3322 of themaster inter-device link PHY block 3318. Each PCS and controller 3302,3322 includes a sequencer 3402, 3422 and a memory 3404, 3424. Each ofthe sequencers 3402, 3422 may be a microprocessor, microcontroller,digital signal processor (DSP), or other processing circuitry. Thememory 3403, 3405 may be a multibank memory, such as a synchronousdynamic random access memory (SDRAM), or any other multibank componentcapable of retrieving and storing information.

The PCS and controller 3302 includes the sequencer 3402. The sequencer3402 is connected to the memory 3403. The connections between thesequencer 3402 and the memory 3403 include an address bus 3408, a databus 3410, and a control bus 3412. The data bus 3410 may be used to readdata and write data between the sequencer 3402 and the memory 3403. Thecontrol bus 3412 may include signals used to control the writing of datafrom the sequencer 3402 to the memory 3403. The control bus 3412 mayinclude signals used to control the reading of data from the memory 3403to the sequencer 3402. For example, the control bus 3412 may includesignals such as a read signal and a write signal. The read signal may bea single signal line that indicates when the memory is being read by thesequencer 3402. The write signal may be a single signal line thatindicates when the memory is being written by the sequencer 3402. Insome examples the control bus 3412 may also include a bite enablesignal. The bite enable signal may be a group of signal lines thatindicate the size of the data, e.g., 8, 16, 32, 64 bytes. In someexamples however, the size of the data may be fixed, e.g., 64 bytes.Accordingly, the bite enable signal may be optional on the control bus3412.

Other optional signals that may be part of the control bus 3412 include,but are not limited to, transfer acknowledgment (ACK), bus request, busgrant, interrupt request, clock signals, and reset signals. The transferacknowledge signal may indicate that data is acknowledged by a device,e.g., the sequencer 3402, as being read. The bus request may indicatethat a device, e.g., the sequencer 3402 or the memory 3403 is requestingthe bus, e.g., use of the address bus 3408 and one of the write data bus3410 or the read data bus 3410. The bus grant may indicate that thesequencer 3402 has granted access to the bus. The interrupt request mayindicate to the sequencer 3402 that a lower priority device isrequesting the bus. Any clock signals on the control bus 3412 may beused to synchronize devices on the control bus 3412 such as thesequencer 3402, the memory 3403, or both.

The reset may be used to reset the sequencer 3402, the memory 3403, orboth. Typically the reset may be used to reset the sequencer 3402. Thesignals described above as optional are generally not used in theexample system described below, but may be used in a particularimplementation of the systems and methods described.

The address bus 3408 may be used to indicate an address within thememory 3403 which the sequencer is reading or writing. For example, ifthe sequencer 3402 wishes to read a memory location in the memory 3403the sequencer may output the address of the memory location on theaddress bus 3408. Additionally, the sequencer 3402 may drive the readsignal active. The read signal may be part of the control bus 3412. Thememory 3403 may then output the data in the memory location indicated bythe address bus 3408 on the data bus 3410. Similarly, if the sequencer3402 wishes to write a memory location in the memory 3403, the sequencermay output the address of the memory location on the address bus 3408.Additionally, the sequencer 3402 may drive the write signal active. Thewrite signal may be part of the control bus 3412. The sequencer 3402 maydrive the data bus 3410 with the data that is to be written to thememory 3403. The sequencer 3402 may drive the write data bus 3410 withthe data that is to be written to the memory 3403 at the address on theaddress bus 3408.

As illustrated in FIG. 34, the sequencer 3402 may also access a datamultiplexer 3406 that may send and receive data. In some examples, thesequencer 3402 may read data from the uplink and write data to thedownlink using the data multiplexer 3406. In some examples, data fromthe data multiplexer 3406 may be written to the memory 3403. In someexamples, data from the memory 3403 may be written to the datamultiplexer 3406. In some examples, the data multiplexer 3406 may beconfigured to loop received data to one or more transmit outputs of thedata multiplexer.

The PCS and controller 3322 includes the sequencer 3422. The sequencer3422 is connected to the memory 3403. The connections between thesequencer 3422 and the memory 3403 include an address bus 3428, a databus 3420, and a control bus 3432. The data bus 3430 may be used to readdata and write data between the sequencer 3422 and the memory 3403. Thecontrol bus 3432 may include signals used to control the writing of datafrom the sequencer 3422 to the memory 3403. The control bus 3432 mayinclude signals used to control the reading of data from the memory 3403to the sequencer 3422. For example, as discussed above, the control bus3432 may include signals such as a read signal, a write signal, and abite enable signal (optional). Other optional signals that may be partof the control bus 3412 include, but are not limited to, transferacknowledgment (ACK), bus request, bus grant, interrupt request, clocksignals, and reset signals.

The address bus 3428 may be used to indicate within the memory 3403where the sequencer is reading or writing. For example, if the sequencer3422 wishes to read a memory location in the memory 3403 the sequencermay output the address of the memory location on the address bus 3428.Additionally, the sequencer 3422 may drive read signal active. The readsignal may be part of the control bus 3432. The memory 3403 may thenoutput the data in the memory location indicated by the address bus 3428on the read data bus 3430. Similarly, if the sequencer 3422 wishes towrite a memory location in the memory 3403, the sequencer may output theaddress of the memory location on the address bus 3408. Additionally,the sequencer 3422 may drive the write signal active. The write signalmay be part of the control bus 3432. The sequencer 3422 may drive thewrite data bus 3430 with the data that is to be written to the memory3403 at the address on the address bus 3428.

As illustrated in FIG. 34, the sequencer 3422 may also access a datamultiplexer 3426 that may send and receive data. In some examples, thesequencer 3422 may read data from the uplink and write data to thedownlink using the data multiplexer 3426. In some examples, data fromthe data multiplexer 3426 may be written to the memory 3403. In someexamples, data from the memory 3403 may be written to the datamultiplexer 3426. In some examples, the data multiplexer 3426 may beconfigured to loop received data to one or more transmit outputs of thedata multiplexer.

FIG. 35 is an example high-speed serial transceiver apparatus 3500 withprogrammable distributed data processing functionality in accordancewith various embodiments. Transceiver apparatus 3500 can include aningress channel 3501 that processes serial data received by thetransceiver apparatus, and an egress channel 3503 that processes datafor serial transmission by the transceiver apparatus. Transceiverapparatus 3500 can also include a transport layer 3505 (such aspacketization layer 802 of FIG. 8), a link layer 3507 (such as linklayer 804 of FIG. 8), and a PHY 3509 (such as PHY 806 of FIG. 8). Asshown in FIG. 35 at the overlap of transport layer 3505 and ingresschannel 3501, the transport layer can include transport-layer ingresselements (TIEs) 3511, which are elements of the transport layer thatprocess data in the ingress channel. Likewise, as shown in FIG. 35 atthe overlap of transport layer 3505 and egress channel 3503, thetransport layer can include transport-layer egress elements (TIEs) 3513,which are elements in the transport layer that process data in theegress channel. Transceiver apparatus 3500 can also include. Similarly,link layer 3507 can include link-layer ingress elements (LIEs) 3515 thatprocess data in the ingress channel and link-layer egress elements(LEEs) 3517 that process data in the egress channel. PHY 3509 caninclude PHY ingress elements (PIEs) 3519 that process data in theingress channel and PHY egress elements (PEEs) 3521 that process data inthe egress channel. Some examples of ingress elements and egresselements can include packetizers, de-packetizers, aligners,transmitters, receivers, buffers, registers, etc.

Transceiver apparatus 3500 can also include a programmable controller3523 that can execute computer-executable code to perform variousoperations. Programmable controller 3523 can be reprogrammed via acontrol interconnect 3525. For example, computer-executable code storedin programmable controller 3523 can be modified, updated, etc., viacontrol interconnect 3525. Programmable controller 3523 can communicatevia control interconnect 3525, for example, to report results oftesting, report errors, etc., as will be discussed in more detail below.

Programmable controller 3523 can be connected to transport layer 3505via transport layer interconnect 3527, which can allow the programmablecontroller to communicate with the elements of the transport layer thatprocess channel data, such as TIEs 3511 and TEEs 3513. Programmablecontroller 3523 can be connected to link layer 3507 via link layerinterconnect 3529, which can allow the programmable controller tocommunicate with the elements of the link layer that process channeldata, such as LIEs 3515 and LEEs 3517. Programmable controller 3523 canbe connected to PHY 3509 via PHY interconnect 3531, which can allow theprogrammable controller to communicate with the elements of the PHY thatprocess channel data, such as PIEs 3519 and PEEs 3521.

The interconnects between programmable controller 3523 and the variousdata processing elements of transport layer 3505, link layer 3507, andPHY 3509 can allow the programmable controller to utilize the dataprocessing functionality of these elements to process data. In otherwords, data processing tasks can be distributed among programmablecontroller 3523, data processing elements of transport layer 3505, dataprocessing elements of link layer 3507, and data processing elements ofPHY 3509. Thus, connection of programmable controller 3523, at least onedata processing element of one of the three layers, and at least onedata processing element of another of the three layers can form thestructure of a programmable distributed data processor. In this way, forexample, programmable controller can offload data processing work, whichcan allow the programmable controller to be smaller and to operatefaster. Furthermore, because the distributed data processing isaccomplished by elements in ingress channel 3501 and/or egress channel3503, programmable controller 3523 can be specialized to analyze,adjust, test, diagnose, control, etc., these elements efficiently andquickly. This can provide advantages particularly in high-speed,low-power serial transceivers.

As shown in FIG. 35, the interconnects can create various dataprocessing paths over which programmable controller 3523 can send data.For example, programmable processor 3523 can send data through a datapath 3533, which includes transport layer interconnect 3527, one or moreof TEEs 3513, the part of egress channel 3503 between transport layer3505 and link layer 3507, one or more of LEEs 3517, and link layerinterconnect 3529 to the programmable controller.

Another processing path, data path 3535, can include transport layerinterconnect 3527, one or more of TEEs 3513, the part of egress channel3503 between transport layer 3505 and link layer 3507, one or more ofLEEs 3517, the part of egress channel 3503 between link layer 3507 andPHY 3509, one or more PEEs 3521, and PHY interconnect 3531 to theprogrammable controller. Another processing path, data path 3537, caninclude link layer interconnect 3529, one or more of LEEs 3517, the partof egress channel 3503 between link layer 3507 and PHY 3509, one or morePEEs 3521, and PHY interconnect 3531 to the programmable controller.

Some data paths can utilize the data processing elements of a singlelayer only. For example, in a data path 3539, programmable controller3523 sends data through link layer interconnect 3529 to be processed byone or more LEEs 3517, and the processed data is returned to theprogrammable processor through the link layer interconnect. Similarprocessing paths can exist for data processing using only TIEs 3511,only TEEs 3513, only LIEs 3515, only PIEs 3519, or only PEEs 3521.

Some processing paths do not return to programmable controller 3523. Forexample, programmable controller 3523 can send data through PHYinterconnect 3531 to be processed by one or more PEEs 3521 andtransmitted as transmitted data 3541. Likewise, programmable controller3523 can send data through link layer interconnect 3529 to be processedby one or more LEEs 3517, sent to one or more PEEs 3521 for furtherprocessing, and transmitted as transmitted data 3541. Similarly,programmable controller can send data through transport layerinterconnect 3527 to be processed by one or more TEEs 3513, sent to oneor more LEEs 3517 for further processing, sent to one or more PEEs 3521for further processing, and transmitted as transmitted data 3541.

Some processing paths utilize data processing elements in ingresschannel 3501. For example, a data path 3543 can include PHY interconnect3531, one or more PIEs 3519, the part of ingress channel 3501 betweenPHY 3509 and link layer 3507, one or more LIEs 3515, and link layerinterconnect 3529. A data path 3545 can include PHY interconnect 3531,one or more PIEs 3519, the part of ingress channel 3501 between PHY 3509and link layer 3507, one or more LIEs 3515, the part of the ingresschannel between link layer 3507 and transport layer 3505, one or moreTIEs 3511, and transport layer interconnect 3527. A data path 3547 caninclude data layer interconnect 3529, one or more LIEs 3515, the part ofthe ingress channel between link layer 3507 and transport layer 3505,one or more TIEs 3511, and transport layer interconnect 3527.

In addition, programmable controller 3523 can intercept received data3549 at various points of processing, e.g., after processing in PIEs3519, LIEs 3515, or TIEs 3511. In various embodiments, received data3549 can be sent from another transceiver apparatus that includes aprogrammable distributed data processor. In this case, received data3549 can include data processed by distributed data processing accordingto the present disclosure, and interception by programmable controller3523 can be a part of the distributed processing, as described in moredetail in one example of FIG. 36.

Programmable controller 3523 can send control signals to the variouselements in transport layer 3505, link layer 3507, and PHY 3509. In somecases, for example, control signals can be sent to control the elementsto process the data as discussed above. In other cases, the dataprocessing is performed by the elements without specific control signalsfrom programmable controller 3523. In other words, programmablecontroller 3523 can simply inject the data and the elements process itas part of normal operation of ingress channel 3501 and/or egresschannel 3503. In various embodiments, the control signals can be sentvia the same paths as the data, such as interconnects 3527, 3529, and3531. In various embodiments, control signals can be sent via separate,dedicated control paths (not shown). Control signals from programmablecontroller 3523 can also be used to control the operation of variouselements in the layers, such as, for example, turning transmitterson/off, resetting elements, updating parameters of elements, etc. Thesecontrols may be based, for example, on data processed by the elements.For example, programmable controller 3523 may send a test packet to beprocessed and, based on the results of the processing, may send acontrol signal to adjust a parameter to improve transmission.

FIG. 36 is an example high-speed serial link apparatus 3600 withprogrammable distributed data processing functionality in accordancewith various embodiments. Link apparatus 3600 can include a link master3601 and a link slave 3603. Link master can include a sequencer 3605 anda sequencer memory 3607, which operate as a programmable controller,such as programmable controller 3523 of FIG. 35. Likewise, link slavecan include a sequencer 3609 and a sequencer memory 3611, which operateas a programmable controller, such as programmable controller 3523 ofFIG. 35.

In various embodiments, link slave 3603 can be an RFIC, and link master3601 can be a BBIC. Link apparatus 3600 can include a data uplinkchannel that includes an egress channel of link master 3601, includingLEEs, such as an egress buffer (eBuf) 3613 that can receive data from amemory interconnect 3615, and a packetizer 3617, and TEEs, such as atransmitter block 3619 (which can include an asynchronousfirst-in-first-out (fifo) buffer), and a transmitter 3621 (which caninclude a parallel-to-serial (P2S) converter). The data uplink channelcan also include an ingress channel of link slave 3603, including TIEs,such as a receiver 3623 (which can include a serial-to-parallel (S2P)converter), and a receiver block 3625 (which can include an asynchronousfifo and an aligner), and LIEs, such as a de-packetizer 3627, and aningress buffer (iBuf) 3629, which can send data to a de-multiplexer(de-mux) 3631.

Link apparatus 3600 can include a data downlink channel that includes anegress channel of link slave 3603, including LEEs, such as an eBuf 3633that can receive data from an arbiter 3635, and a packetizer 3637, andTEEs, such as a transmitter block 3639 (which can include anasynchronous fifo buffer), and a transmitter 3641 (which can include aP2S converter). The data downlink channel can also include an ingresschannel of link master 3601, including TIEs, such as a receiver 3643(which can include a S2P converter), and a receiver block 3645 (whichcan include an asynchronous fifo and an aligner), and LIEs, such as ade-packetizer 3647, and an iBuf 3649, which can send data to memoryinterconnect 3615.

A link layer interconnect 3651 can connect sequencer 3609 of link slave3603 to signal lines into and out of, respectively, eBuf 3633 and iBuf3629. A link layer interconnect 3653 can connect sequencer memory 3611to a signal line from de-packetizer 3627 to iBuf 3629 and to a signalline from eBuf 3633 to packetizer 3637. An interconnect 3655 can connectsequencer memory 3611 to a signal line from receiver block 3625 tode-packetizer 3627. It should be noted that interconnect 3655 servesboth as a data layer interconnect and a PHY interconnect. Specifically,interconnect 3655 allows sequencer memory 3611 to send data tode-packetizer 3627 (a link layer data processing element) and to receivedata from receiver block 3625 (a PHY data processing element). In thisregard, interconnect 3655 is a dual-layer interconnect. Likewise, aninterconnect 3657 can allow sequencer memory 3611 to send data totransmitter block 3639 and to receive data from packetizer 3637. Thus,interconnect 3657 is also a dual-layer interconnect.

A link layer interconnect 3659 can connect sequencer 3605 of link master3601 to signal lines into and out of, respectively, eBuf 3613 and iBuf3649. A link layer interconnect 3661 can connect sequencer memory 3607to a signal line from de-packetizer 3647 to iBuf 3649 and to a signalline from eBuf 3613 to packetizer 3617. An interconnect 3663 can connectsequencer memory 3607 to a signal line from receiver block 3645 tode-packetizer 3647. An interconnect 3665 can connect sequencer memory3607 to a signal line from packetizer 3617 to transmitter block 3619.

Sequencer 3605 of link master 3601 and sequencer 3609 of link slave 3603can communicate via a sideband, which includes sideband lines 3667A onthe link master's side and sideband lines 3667B on the link slave'sside.

While FIGS. 33-36 illustrate various embodiments of the physicalstructures, e.g., programmable controller, interconnects, layerelements, etc., that can be included in programmable distributed dataprocessors, various examples of operations and functionality that can beperformed by programmable distributed data processors will now bedescribed with reference to FIGS. 37-41.

FIG. 37 is a diagram illustrating an example representation of a linkkernel of computer instructions that can be executed by a programmabledistributed data processor in accordance with various embodiments. Thedata processing paths of a reprogrammable distributed data processorutilized by the following examples will be readily understood by oneskilled in the art in light of the foregoing description of the physicalstructures of such a system, therefore, a detailed description of thespecific data processing paths will not be provided. In variousembodiments, the programmable controller can create data processingpaths from transport layer to transport layer, which can be used forflow control, error messaging, diagnostics. In various embodiments, dataprocessing paths from SEQ MEM to link layer or PHY layer can be used forequalization by injecting patterns, and can be used for training throughinjecting patterns. In various embodiments, intercepting at data signalsat a receiver PHY or link layer (after de-packetizer) can be used forequalization and/or training. In various embodiments, error patterns canbe injected and error counts checked at another location along dataprocessing paths. In various embodiments, a raw bitstream can becaptured in SEQ MEM for logical analyzer diagnostic, which can be usedto diagnose complex faults, such as system faults.

Diagram 3700 includes an outer ring 3702 that represents the softwarestack. At the software stack level the inter-device link may performvarious sanity tests such as loopback tests. The software stack includesdebugging tools for low-level tests and management software. At thesoftware stack level power management, error recovery and debugging toolsets may also reside.

The diagram also includes a data layer 3704 for flow control, errorhandling, and inter-device link debugging, including pinging. Theinter-device link protocol data layer may impact power management usingflow control, may implement error handling, and may implement testingusing the ping feature.

In the PCS layer 3706, power management may be impacted by starting orstopping of links. Additionally, loopback test and the error handlingmay be implemented at the PCS layer. The PCS layer 3706 may includeautomatic testing using digital loopback, bit error rate testing,loopback testing of analog and digital circuitry, pattern injection,physical layer start and stop, boot and, power modes.

The physical layer SERDES 3708 may implement SERDES test andcharacterization jitter tolerance transmit and receive measurements,built in self test, error injection and other testing.

For example, some errors can include link lock errors, which can beidentified when one party repeatedly receives NACKs for messages sent,or repeatedly transmits without receiving an ACK. For example, in a casethat master sends to slave, but slave repeatedly sends NACKs inresponse, it is likely that master Tx to slave Rx lane has lost lock. Torecover from this error condition, master can indicate transition tolink power down/hibernate using link_en, and then can indicatetransition to link power up in order to re-acquire lock. Anotherpossible error condition is when slave sends to master, master sendsACKS in response, but master sees that slave is repeating. In this case,it is likely that master Tx to slave Rx lane has lost lock. To recoverfrom this error condition, master can indicate transition to link powerdown/hibernate using link_en, and then can indicate transition to linkpower up in order to re-acquire lock. Another possible error conditionis when slave sends to master, master doesn't receive, so slave repeats,and slave keeps trying indefinitely. In this error condition, it islikely that slave Tx to master Rx lane has lost lock. One method ofrecovery can be to signal to master out of band. If there is an out ofband mechanism available, slave can signal to master that the linkshould be reset by transitioning to link power down and back again.However, if slave does not have a mechanism to signal to the master outof band, the slave should keep trying.

Some errors can include state transition errors. For example, an errorcan occur during device power up, e.g., transition from QL2 to QL1. Inthis case, if master waits for alignment to indicate transition iscomplete, and master doesn't receive alignment in allotted time, slavehas not powered up correctly. Master can inform top level controller(for power cycling). An error can occur during the first ping, e.g.,QL1. If master does not receive ping from slave, then link power down/upusing link_en should be tried. If that fails, master should inform toplevel controller (for power cycling). An error can occur during a speedchange from QL1 to QL0, or vice versa. If master does not receive pingfrom slave, then link power down/up using link_en should be tried.However, it may not be clear which mode to ‘hibernate’ to, e.g., highspeed or low speed. In this case, low speed should be the default atthis time. If that fails, master should inform top level controller (forpower cycling). An error can occur during link power down, e.g., QL0 toQL0p, or QL1 to QL1p. For example, master requests power-down viamessage and does not receive an ACK, and master retries. It is mandatoryfor slave to comply. If slave is not acknowledging transition then thisis treated as a fatal error and top controller should be informed. Anerror can occur during link power up, e.g., QL0p to QL0, or QL1p to QL1.For example, master requests link power-up via link_en, but cannotcomplete sequence through to ping/ACK. In this case, master retries, ifpossible. It is mandatory for slave to comply. If slave is notacknowledging transition then this is treated as a fatal error and topcontroller should be informed. An error can occur when slave requestslink power-up via link_req, but cannot complete sequence through toping/ACK. In this case, slave retries, if possible. Other than that,there is not much that slave can do about it.

Some errors can occur during test modes. For example, during a link testmode, e.g., QL0l or QL1l, when slave is looping back, master may see alarge error count. In this case, master can move link to link-power-downand back again. In some cases, when master is looping back, slave maysee a large error count. In this case, if the link is timed, slave waitsuntil the time is up and then reports errors to master. If the link isnot timed, and in-band signaling is still monitored by master, slaveindicates errors to master.

In various embodiments, testing and debugging can be performed by aprogrammable distributed data processing system. Some examples oftesting and debugging are described below. In an external loopback mode,the sequencer can be programmed, for example, to one of three loopbackoptions. A clock can be provided for RFIC because RFIC SERDES does notgenerate its own clock. This mode can be used to measure jittertolerance including Physical Layer and PCS Layer. In the link loopbackmode, the SERDES receive data (RX) can be routed back to the SERDEStransmit data (TX). The loopback data path is routed from the output ofthe RX async fifo to the input of TX asynch fifo. This can be enabled oneither BBIC or RFIC. Only one of the three RX/TX lanes can be enabled;hence lane number parameters are used to configure the lane selection.This mode is used by the tester or scope to verify the data aretraveling cleanly across SERDES RX/TX and QL async fifo. There are noexit transition to other mode/state. Must power off/reset in order toswitch to other modes.

The clock has to be provided by the external equipment, tester, or labequipment because the RFIC SERDES does not generate its clock. This testcan be used in LS or HS mode, depending on the external clock. Aninternal RFIC clock, wmss_clk, can be setup according to a clock setupprocedure.

Thus, programmable distributed data processors can be programmed toperform, for example, boot up sequence management, power management,testing, initiation of the physical layer link, bit alignment of asignal received by a receiver, bit alignment of a signal transmitted bya transmitter, training, loop-back modes, debugging modes, errorhandling, □phase-locked-loop (PLL) initialization, and reset handling.

Some further examples of boot up sequence management performed by aprogrammable distributed data processor can include insertion ofequalization and synchronization bursts for the SERDES, side bandcommunication, e.g., one side band signal in each direction to provide amechanism for reset/wake and error recovery (e.g., link_en and link_reqcan be used for wakeup signaling), training sequences for fast wakeup,hibernate wake-up, initial boot and recovery, involving equalization,CDR and alignment (distributed data processing can handle all trainingsequences and timing), low speed (LS) mode and high speed (HS) modehandling (the PHY can handles the packetization and de-packetization ofSERDES data from/into blocks of data that can be further processed bythe physical layer and upper layers, programmable Tx amplitudes (Txparameters can be reprogrammed by distributed data processing based onfield conditions), multiple TX and Rx termination settings can be used,multiple power states can be programmed for boot up, signal detectionduring boot up, CDR on and off times can be set, multiple calibrated PLLsettings for fast frequency switching can be used (two sideband signalscan be used to control the operation states of the serial interconnect,e.g. link_en and link_req).

Some further examples of power management performed by a programmabledistributed data processor can include adjusting transmission credit,and sending power management messages. For example, ACK messages can beused for credit-based flow control communication. Flow control occursindependently between MSG and DATA channels of the frame package. ACKmessages serve two purposes: flow control and error management. Aprogrammable controller get notified when an ACK message is received andcan decide to go into various power management states or stay awake dueto various usages or power management schemes, and can send instructionsto the various elements to adjust power states.

Some further examples of testing performed by a programmable distributeddata processor can include pinging operations to separate bit error rate(BER) profiling at the PHY and DLL layer. While bit detection andmonitoring can be done by other dedicated hardware, the errorhandling/testing report mechanisms can be handled by a distributed dataprocessor. Test patterns can be generated and programmed by adistributed data processor. A control register bus can be managed by adistributed data processor.

Some further examples of initiation of a PHY link performed by aprogrammable distributed data processor can include 128b/130b encodingby providing sync symbol insertion differentiating between PHY burst(physical layer communication) or DLL burst, switching between PHY andDLL burst modes can be controlled/managed by a distributed dataprocessor, equalization (the start of the EQ sequence can handled by adistributed data processor), a PHY burst mode, and a packet burst mode.

Some further examples of training performed by a programmabledistributed data processor can include injecting custom packets to trainlinks, and adding physical layer framing tokens to the DLL packetstream.

Some further examples of error handling performed by a programmabledistributed data processor can include enforcing PHY layer framing rulesat the receiver (frame rules can be detected by PHY layer hardware andcan be reported back to a programmable controller for decision making,and, e.g., the controller can ignore, react, or wait until theappreciate time to reset the link), framing and alignment of receivedbit stream, channel identification (ID), which can be protected bycyclic redundancy check (CRC). In some examples, a bulk acknowledgescheme, in which an ACK MSG is sent once the credit for the trafficclass has been exhausted, a programmable controller can change thefrequency of ACK message sent by the downstream/receiver.

FIGS. 38-41 illustrate example tests that can be performed by aprogrammable distributed data processor in accordance with variousembodiments.

FIG. 38 illustrates an example slave external loopback testing mode inwhich a scope 3801 provides a clock signal to link slave 3603, andprovides a testing signal to receiver 3623. Sequencer 3609 sends controlsignals via interconnect 3655 to control the asynchronous fifo ofreceiver block 3625 to provide the data received from receiver 3623 tothe asynchronous fifo of transmitter block 3639, and sends controlsignals via interconnect 3657 to transmitter 3641 to control thetransmitter to receive the data. Transmitter 3641 retrieves the data andtransmits the data to scope 3801 to be analyzed. In this way, forexample, sequencer 3609 can control a loopback testing that testsreceiver 3623 and transmitter 3641.

FIG. 39 illustrates an example slave internal loopback testing mode inwhich a clock 3901 can provide a clock signal to link slave 3603, andsequencer 3609 can control transmitter block 3639 to read test data fromsequencer memory 3611 via interconnect 3657. Transmitter block 3639 canthen send the test data to transmitter 3641. Sequencer 3609 can controltransmitter 3639 to send the test data to receiver 3623, can control thereceiver to send the test data to receiver block 3625, and can controlthe receiver block to send the test data to sequencer memory 3611 viainterconnect 3655. In this way, for example, distributed data processingcan be used to test transmitter block 3639, transmitter 3641, receiver3623, and receiver block 3625. In this example, only one Tx lane isselected but it is possible to select any of the Tx lanes to perform thetest. For each loopback it is possible to select the level of the loop,this selection can be controlled through SERDES CSR. The loop is closedoutside the IC at the board level. The loop is closed internally to theIC at the SERDES buffer level (using SERDES CSRs). This test can includean internal Bit-Error-Rate BER test, in which a test pattern isself-generated and verified internally while SERDES path is beingconfigured in loopback mode. An LFSR data pattern can be generated andsent out on TX Lane to SERDES TX block via async fifo. A SERDES loopbackmode can be enabled. TX data on one of the lanes can be looped back toan RX block. At least two options can be used. In a first option,sequencer can send a fix idle token, and the scrambler/de-scrambler(LSFR) can be enabled. In a second option, the sequencer can send apre-loaded pattern (PRBS x), and the scrambler/de-scrambler can bedisabled.

FIG. 40 illustrates an example master internal loopback testing mode inwhich sequencer 3605 can control transmitter block 3619 to read testdata from sequencer memory 3607 via interconnect 3665. Transmitter block3619 can send the test data to transmitter 3621, and sequencer 3605 cancontrol the transmitter to send the test data to receiver 3643, cancontrol the receiver to send the test data to receiver block 3645, andcan control the receiver block to send the test data to sequencer memory3607 via interconnect 3663. In this way, for example, distributed dataprocessing can be used to test transmitter block 3619, transmitter 3621,receiver 3643, and receiver block 3645.

FIG. 41 illustrates an example link-to-link loopback testing mode inwhich sequencer 3605 of link master 3601 can set a test data pathincluding interconnect 3665, transmitter block 3619, transmitter 3621,receiver 3643, receiver block 3645, and interconnect 3663. Sequencer3605 can send control signals via sideband 3667A and 3667B to instructsequencer 3609 of link slave 3603 to control various elements of thelink slave in order to complete the test data path. In response to theinstructions, sequencer 3609 can set the remainder of the test data pathto include receiver 3623, receiver block 3625, interconnect 3655,interconnect 3657, transmitter block 3639, and transmitter 3641. In thisway, for example, sequencer 3605 of link master 3601 can cause test datato be read from sequencer memory 3607, sent along the illustrated dataprocessing path to sequencer memory 3611 of link slave 3603, read fromthe sequencer memory of the link slave, and sent back to sequencermemory 3607 of the link master. In this test, a remote/end-to-endBit-Error-Rate (BER) mode can perform a comprehensive bit error rateanalysis end-to-end. The test pattern can be sent across all TX DLs, andthe BER analysis can be collected independently on either UL or DL, orboth. The test pattern can be configured in both a boot mode and a highspeed mode. A LFSR data pattern can be generated and sent out across allmajor components: TX async fifo, SERDES TX block, pad, board wire,SERDES RX block, RX async fifo and SEQ MEM, for example.

It is understood that the specific order or hierarchy of blocks in theprocesses/flowcharts disclosed is an illustration of exemplaryapproaches. Based upon design preferences, it is understood that thespecific order or hierarchy of blocks in the processes/flowcharts may berearranged. Further, some blocks may be combined or omitted. Theaccompanying method claims present elements of the various blocks in asample order, and are not meant to be limited to the specific order orhierarchy presented.

The previous description is provided to enable any person skilled in theart to practice the various aspects described herein. Variousmodifications to these aspects will be readily apparent to those skilledin the art, and the generic principles defined herein may be applied toother aspects. Thus, the claims are not intended to be limited to theaspects shown herein, but is to be accorded the full scope consistentwith the language claims, wherein reference to an element in thesingular is not intended to mean “one and only one” unless specificallyso stated, but rather “one or more.” The word “exemplary” is used hereinto mean “serving as an example, instance, or illustration.” Any aspectdescribed herein as “exemplary” is not necessarily to be construed aspreferred or advantageous over other aspects. Unless specifically statedotherwise, the term “some” refers to one or more. Combinations such as“at least one of A, B, or C,” “one or more of A, B, or C,” “at least oneof A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or anycombination thereof” include any combination of A, B, and/or C, and mayinclude multiples of A, multiples of B, or multiples of C. Specifically,combinations such as “at least one of A, B, or C,” “one or more of A, B,or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and“A, B, C, or any combination thereof” may be A only, B only, C only, Aand B, A and C, B and C, or A and B and C, where any such combinationsmay contain one or more member or members of A, B, or C. All structuraland functional equivalents to the elements of the various aspectsdescribed throughout this disclosure that are known or later come to beknown to those of ordinary skill in the art are expressly incorporatedherein by reference and are intended to be encompassed by the claims.Moreover, nothing disclosed herein is intended to be dedicated to thepublic regardless of whether such disclosure is explicitly recited inthe claims. The words “module,” “mechanism,” “element,” “device,” andthe like may not be a substitute for the word “means.” As such, no claimelement is to be construed as a means plus function unless the elementis expressly recited using the phrase “means for.”

What is claimed is:
 1. A method of a master device for transmission ofdata over a serial link using a unidirectional clock signal, the methodcomprising: generating the unidirectional clock signal based on a firstclock of the master device; sending the unidirectional clock signal to aslave device that is connected to the serial link; and transmitting datato the slave device over the serial link based on the first clock. 2.The method of claim 1, wherein the unidirectional clock is generated tohave a same rate as the first clock.
 3. The method of claim 1, whereinthe unidirectional clock signal is generated such that a rate of theunidirectional clock signal is a fraction of a rate of the first clock.4. The method of claim 1, wherein the unidirectional clock signal issent over the serial link to the slave device.
 5. The method of claim 1,wherein the unidirectional clock signal is sent over a sideband to theslave device.
 6. A method of a slave device for transmission of dataover a serial link using a unidirectional clock signal, the methodcomprising: receiving the unidirectional clock signal from a masterdevice, wherein the unidirectional clock signal is based on a firstclock of the master device; and transmitting data over the serial linkto the master device based on the unidirectional clock signal.
 7. Themethod of claim 6, wherein a rate of the unidirectional clock is thesame as a rate of the first clock.
 8. The method of claim 6, wherein arate of the unidirectional clock signal is a fraction of a rate of thefirst clock.
 9. The method of claim 6, wherein the unidirectional clocksignal is received over the serial link from the master device.
 10. Themethod of claim 6, wherein the unidirectional clock signal is receivedover a sideband from the master device.
 11. An apparatus that transmitsdata over a serial link using a unidirectional clock signal, theapparatus comprising: a master device including a first clock, a clocksignal generator that generates the unidirectional clock signal based onthe first clock, and a transmitter component that sends theunidirectional clock signal to a slave device that is connected to theserial link and that transmits data to the slave device over the seriallink based on the first clock.
 12. The apparatus of claim 11, whereinthe clock signal generator generates the unidirectional clock to have asame rate as the first clock.
 13. The apparatus of claim 11, wherein theclock signal generator generates the unidirectional clock such that arate of the unidirectional clock signal is a fraction of a rate of thefirst clock.
 14. The apparatus of claim 11, wherein the transmittercomponent transmits the unidirectional clock signal over the serial linkto the slave device.
 15. The apparatus of claim 11, wherein thetransmitter component transmits the unidirectional clock signal over asideband to the slave device.
 16. An apparatus that transmits data overa serial link using a unidirectional clock signal, the apparatuscomprising: a slave device including a receiver that receives theunidirectional clock signal from a master device, wherein theunidirectional clock signal is based on a first clock of the masterdevice, and a transmitter that transmits data over the serial link tothe master device based on the unidirectional clock signal.
 17. Theapparatus of claim 16, wherein a rate of the unidirectional clock is thesame as a rate of the first clock.
 18. The apparatus of claim 16,wherein a rate of the unidirectional clock signal is a fraction of arate of the first clock.
 19. The apparatus of claim 16, wherein thereceiver receives the unidirectional clock signal over the serial linkfrom the master device.
 20. The apparatus of claim 16, wherein thereceiver receives the unidirectional clock signal over a sideband fromthe master device.